Emmons, Hamilton Scheduling to a common due date on parallel uniform processors. (English) Zbl 0648.90043 Nav. Res. Logist. 34, No. 6, 803-810 (1987). Summary: We consider scheduling a set of jobs on parallel processors, when all jobs have a common due date and earliness and lateness are penalized at different cost rates. For identical processors, the secondary criteria of minimizing makespan and machine occupancy are addressed. The extension to different, uniform processors is also solved. Cited in 1 ReviewCited in 46 Documents MSC: 90B35 Deterministic scheduling theory in operations research Keywords:parallel processors; common due date; minimizing makespan; machine occupancy; uniform processors PDFBibTeX XMLCite \textit{H. Emmons}, Nav. Res. Logist. 34, No. 6, 803--810 (1987; Zbl 0648.90043) Full Text: DOI References: [1] Bagchi, Naval Research Logistics Quarterly 33 pp 227– (1986) [2] Hall, Naval Research Logistics Quarterly 33 pp 49– (1986) [3] Kanet, Naval Research Logistics Quarterly 28 pp 643– (1981) [4] Panwalkar, Operations Research 30 pp 391– (1982) This reference list is based on information provided by the publisher or from digital mathematics libraries. Its items are heuristically matched to zbMATH identifiers and may contain data conversion errors. In some cases that data have been complemented/enhanced by data from zbMATH Open. This attempts to reflect the references listed in the original paper as accurately as possible without claiming completeness or a perfect matching.