Result 1 to 20 from 110 total
A scalable design methodology for energy minimization of STTRAM: A circuit and architecture perspective. (English)
IEEE Trans. VLSI Syst. 19, No. 5, 809-817 (2011).
1
io-port 50037569 Vetter, Jeffrey S.;
Glassbrook, Richard;
Dongarra, Jack;
Schwan, Karsten;
Loftis, Bruce;
Mcnally, Stephen;
Meredith, Jeremy S.;
Rogers, James;
Roth, Philip C.;
Spafford, Kyle;
Yalamanchili, Sudhakar
Keeneland: bringing heterogeneous GPU computing to the computational science community (English)
Computing in Science and Engineering 13, No. 5, 90-95 (2011).
2
A framework for dynamically instrumenting GPU compute applications within GPU ocelot (English)
GPGPU, 9 (2011).
3
HyVM (hybrid virtual machines) ‒ efficient use of future heterogeneous chip multiprocessors. (English)
Müller-Schloer, Christian (ed.) et al., Architecture of computing systems ‒ ARCS 2010. 23rd international conference, Hannover, Germany, February 22‒25, 2010. Proceedings. Berlin: Springer (ISBN 978-3-642-11949-1/pbk). Lecture Notes in Computer Science 5974, 1 (2010).
4
Hyvm - hybrid virtual machines - efficient use of future heterogeneous chip multiprocessors (English)
ARCS, 1 (2010).
5
An energy efficient cache design using spin torque transfer (STT) RAM (English)
ISLPED, 389-394 (2010).
6
Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems (English)
PACT, 353-364 (2010).
7
Modeling GPU-CPU workloads and systems (English)
GPGPU, 31-42 (2010).
8
Speculative execution on multi-GPU systems (English)
IPDPS, 1-12 (2010).
9
Dynamic partitioned global address spaces for power efficient DRAM virtualization (English)
Green Computing Conference, 485-492 (2010).
10
High performance non-blocking switch design in 3D die-stacking technology (English)
ISVLSI, 25-30 (2009).
11
Classification of polarimetric SAR data over wet and arid regions of India (English)
IGARSS (3), 892-895 (2009).
12
Analysis of 7 years aqua AMSR-E derived soil moisture data over India (English)
IGARSS (3), 486-489 (2009).
13
A characterization and analysis of PTX kernels (English)
IISWC, 3-12 (2009).
14
A methodology for robust, energy efficient design of spin-torque-transfer RAM arrays at scaled technologies (English)
ICCAD, 474-477 (2009).
15
An utilization driven framework for energy efficient caches. (English)
Sadayappan, Ponnuswamy (ed.) et al., High performance computing ‒ HiPC 2008. 15th international conference, Bangalore, India, December 17‒20, 2008. Proceedings. Berlin: Springer (ISBN 978-3-540-89893-1/pbk). Lecture Notes in Computer Science 5374, 583-594 (2008).
16
Harmony: an execution model and runtime for heterogeneous many core systems (English)
HPDC, 197-200 (2008).
17
An utilization driven framework for energy efficient caches (English)
HiPC, 583-594 (2008).
18
Sharestreams-V: A virtualized QoS packet scheduling accelerator (English)
FCCM, 265-268 (2008).
19
Customized placement for high performance embedded processor caches (English)
ARCS, 69-82 (2007).
20
Result 1 to 20 from 110 total
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