Result 1 to 20 from 20 total
Ichip multiprocessor architecture: techniques to improve throughput and latency (English)
Synthesis Lectures on Computer Architecture: iChip Multiprocessor Architecture: Techniques to Improve Throughput and Latency (2007).
1
Executing Java programs with transactional memory. (English)
Sci. Comput. Program. 63, No. 2, 111-129 (2006).
2
"Software performance tuning with the apple CHUD tools" (English)
IISWC, 1 (2006).
3
The future of microprocessors. (English)
ACM Queue 3, No. 7, 26-29 (2005).
4
Characterization of TCC on chip-multiprocessors (English)
IEEE PACT, 63-74 (2005).
5
TAPE: a transactional application profiling environment (English)
ICS, 199-208 (2005).
6
Transactional Coherence and Consistency: Simplifying Parallel Hardware and Software. (English)
IEEE Micro 24, No.06, 92-103 (2004).
7
Transactional coherence and consistency: simplifying parallel hardware and software (English)
IEEE Micro 24, No. 6, 92-103 (2004).
8
io-port 70080972 Hammond, Lance;
Wong, Vicky;
Chen, Michael K.;
Carlstrom, Brian D.;
Davis, John D.;
Hertzberg, Ben;
Prabhu, Manohar K.;
Wijaya, Honggo;
Kozyrakis, Christos;
Olukotun, Kunle
Transactional memory coherence and consistency (English)
ISCA, 102-113 (2004).
9
Programming with transactional coherence and consistency (TCC) (English)
ASPLOS, 1-13 (2004).
10
Lattice Boltzmann equation calculation of internal, pressure-driven turbulent flow. (English)
J. Phys. A, Math. Gen. 35, No. 47, 9945-9955 (2002).
11
The Stanford Hydra CMP. (English)
IEEE Micro 20, No.02, 71-84 (2000).
12
The Stanford hydra CMP (English)
IEEE Micro 20, No. 2, 71-84 (2000).
13
Improving the performance of speculatively parallel applications on the hydra CMP (English)
International Conference on Supercomputing, 21-30 (1999).
14
Data speculation support for a chip multiprocessor (English)
ASPLOS, 58-69 (1998).
15
A Single-Chip Multiprocessor. (English)
Computer 30, No.09, 79-85 (1997).
16
A single-chip multiprocessor (English)
IEEE Computer 30, No. 9, 79-85 (1997).
17
The hierarchical multi-bank DRAM: A high-performance architecture for memory integrated with processors (English)
ARVLSI, 303-319 (1997).
18
Evaluation of design alternatives for a multiprocessor microprocessor (English)
ISCA, 67-77 (1996).
19
The case for a single-chip multiprocessor (English)
ASPLOS, 2-11 (1996).
20
Result 1 to 20 from 20 total
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