Result 1 to 10 from 10 total
Transaction-level modeling for architectural and power analysis of powerPC and coreConnect-based systems. (English)
Des. Autom. Embed. Syst. 10, No. 2-3, 105-125 (2005).
1
Transaction-level modeling for architectural and power analysis of powerpc and coreconnect-based systems (English)
Design Autom. for Emb. Sys. 10, No. 2-3, 105-125 (2005).
2
Measurements for structural logic synthesis optimizations. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 22, No. 6, 665-674 (2003).
3
SEAS: a system for early analysis of socs (English)
CODES+ISSS, 150-155 (2003).
4
Metrics for structural logic synthesis (English)
IWLS, 1-6 (2002).
5
Metrics for structural logic synthesis (English)
ICCAD, 551-556 (2002).
6
Unifying behavioral synthesis and physical design (English)
DAC, 756-761 (2000).
7
Subsetting behavioral intellectual property for low power ASIP design. (English)
J. VLSI Signal Process. 21, No. 3, 209-218 (1999).
8
Modeling and automating selection of guarding techniques for datapath elements (English)
ISLPED, 182-187 (1999).
9
Assembly of overlapping DNA sequences by a program written in BASIC for 64K CP/M and MS-DOS IBM-compatible microcomputers. (English)
Nucleic Acids Res. 14, No. 1, 517-527 (1986).
10
Result 1 to 10 from 10 total
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