Result 1 to 20 of 232 total
System-level validation. High-level modeling and directed test generation techniques. (English)
New York, NY: Springer (ISBN 978-1-4614-1358-5/hbk; 978-1-4614-1359-2/ebook). xxi, 247~p. EUR~89.95/net; SFR~120.00; \sterling~81.00/hbk (2013).
1
A clustering algorithm for multiprocessor environments using dynamic priority of modules. (English)
Ann. Math. Inform. 38, 99-110 (2011).
2
Generalized avalanche test for stream cipher analysis. (English)
Joye, Marc (ed.) et al., Security aspects in information technology. First international conference, InfoSecHiComNet 2011, Haldia, India, October 19‒22, 2011. Proceedings. Berlin: Springer (ISBN 978-3-642-24585-5/pbk). Lecture Notes in Computer Science 7011, 168-180 (2011).
3
Dynamic reconfiguration of two-level cache hierarchy in real-time embedded systems. (English)
J. Low Power Electron. 7, No. 1, 17-28 (2011).
4
A dynamic web page prediction model based on access patterns to offer better user latency. (English)
Comput. Res. Repos. 2011, Article No. 1102.0684 (2011).
5
Decoding-aware compression of FPGA bitstreams. (English)
IEEE Trans. VLSI Syst. 19, No. 3, 411-419 (2011).
6
Design of a hard real-time multi-core testbed for energy measurement (English)
Microelectronics Journal 42, No. 10, 1176-1185 (2011).
7
Property learning techniques for efficient generation of directed tests (English)
IEEE Trans. Computers 60, No. 6, 852-864 (2011).
8
A (Q, R) model for fuzzified deterioration under cobweb phenomenon and permissible delay in payment (English)
Computers & Mathematics with Applications 61, No. 4, 921-932 (2011).
9
A brief history of multiprocessors and EDA (English)
IEEE Design & Test of Computers 28, No. 3, 96 (2011).
10
Challenges of rapidly emerging consumer space multiprocessors (English)
IEEE Design & Test of Computers 28, No. 3, 52-53 (2011).
11
Guest editors’ introduction: multicore soc validation with transaction-level models (English)
IEEE Design & Test of Computers 28, No. 3, 6-9 (2011).
12
Efficient directed test generation for validation of multicore architectures (English)
ISQED, 276-283 (2011).
13
Planted (l, d) motif finding with allowable mismatches using kernel based approach (English)
ICCCS, 439-442 (2011).
14
Impact of halo implantation on short channel effect in mosfets (English)
ICWET, 1374 (2011).
15
Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems (English)
DAC, 948-953 (2011).
16
Efficient trace data compression using statically selected dictionary (English)
VTS, 14-19 (2011).
17
Architectures for FPGA-based implementation of motion estimation of dynamic obstacles for autonomous robot navigation (English)
CICSyN, 292-297 (2011).
18
Vision based tracking of multiple dynamic obstacles for autonomous robot navigation (English)
CICSyN, 65-71 (2011).
19
Decision ordering based property decomposition for functional test generation (English)
DATE, 167-172 (2011).
20
Result 1 to 20 of 232 total
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