io-port 05890611 Hoya, Katsuhiko;
Takashima, Daisaburo;
Shiratake, Shinichiro;
Ogiwara, Ryu;
Miyakawa, T.;
Shiga, H.;
Doumae, S.M.;
Ohtsuki, S.;
Kumura, Y.;
Shuto, S.;
Ozaki, T.;
Yamakawa, K.;
Kunishima, I.;
Nitayama, A.;
Fujii, S.
A 64-mb chain feram with quad BL architecture and 200 MB/s burst mode. (English)
IEEE Trans. VLSI Syst. 18, No. 12, 1745-1752 (2010).
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