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<item>
  <id>05337278</id>
  <dt>j</dt>
  <an>05337278</an>
  <augroup>
    <au>Wong, F.S.</au>
    <au>Ito, M.R.</au>
  </augroup>
  <ti>A loop-structured switching network.</ti>
  <so>IEEE Trans. Comput. 33, No. 05, 450-455 (1984).</so>
  <py>1984</py>
  <pu>Institute of Electrical and Electronics Engineers (IEEE), Washington, DC</pu>
  <lagroup>
    <la>EN</la>
  </lagroup>
  <ccgroup>
  </ccgroup>
  <utgroup>
    <ut>recirculating networks</ut>
    <ut>deadlock avoidance methods</ut>
    <ut>packet switching</ut>
    <ut>parallel processing architectures</ut>
  </utgroup>
  <cigroup>
  </cigroup>
  <ligroup>
    <li>doi:10.1109/TC.1984.1676462</li>
  </ligroup>
  <abgroup>
    <ab>Summary: This paper describes a novel loop-structured switching network (LSSN) intended for highly parallel processing architectures. With L loops, it can connect up to N = L* log2 L pairs of transmitting and receiving devices using only N/2 two-by-two switching elements; thus, it is very cost-effective in terms of its component count. Its topology resembles that of the indirect binary n-cube network, but a much higher device-to-switch ratio is achieved because all the links between the switches could be used as both transmitting and receiving stations. It has the advantage of incremental extensibility, and-it could avoid store-and-forward deadlocks (SFD) which prevail in other recirculating packet-switched networks. Our simulation studies show that the average throughput rate and delay of LSSN are close to that of other designs despite its relatively low component count.</ab>
    <rv></rv>
  </abgroup>
</item>