Software-level instruction-cache leakage reduction using value-dependence of SRAM leakage in nanometer technologies. (English)
Stenström, Per (ed.), Transactions on High-Performance Embedded Architectures and Compilers III. Berlin: Springer (ISBN 978-3-642-19447-4/pbk). Lecture Notes in Computer Science 6590. Journal Subline, 275-299 (2011).
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RTL power modeling and estimation of sleep transistor based power gating. (English)
J. Embed. Comput. 3, No. 3, 189-196 (2007-2009).
2
Energy-efficient embedded system design at 90nm and below ‒ A system-level perspective. (English)
Labarta, Jesús (ed.) et al., High-performance computing. 6th international symposium, ISHPC 2005, Nara, Japan, September 7‒9, 2005. First international workshop on advanced low power systems, ALPS 2006. Revised selected papers. Berlin: Springer (ISBN 978-3-540-77703-8/pbk). Lecture Notes in Computer Science 4759, 452-465 (2008).
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Statistical performance modeling and optimization. (English)
Found. Trends Electron. Des. Autom. 1, No. 4, 331-480 (2006).
4
Exploiting loop behavior for data cache leakage reduction. (English)
J. Embed. Comput. 1, No. 4, 501-508 (2005).
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