id: 05759767
dt: j
an: 05759767
au: Sinha, Roopak; Roop, Partha S.; Basu, Samik
ti: Soc design approach using convertibility verification.
so: EURASIP J. Embed. Syst. 2008, Article ID 296206, 19 p. (2008).
py: 2008
pu: Springer International Publishing AG, Basel
la: EN
cc: 
ut: 
ci: 
li: doi:10.1155/2008/296206
ab: Summary: Compositional design of systems on chip from preverified
    components helps to achieve shorter design cycles and time to market.
    However, the design process is affected by the issue of protocol
    mismatches, where two components fail to communicate with each other
    due to protocol differences. Convertibility verification, which
    involves the automatic generation of a converter to facilitate
    communication between two mismatched components, is a collection of
    techniques to address protocol mismatches. We present an approach to
    convertibility verification using module checking. We use Kripke
    structures to represent protocols and the temporal logic ACTL to
    describe desired system behavior. A tableau-based converter generation
    algorithm is presented which is shown to be sound and complete. We have
    developed a prototype implementation of the proposed algorithm and have
    used it to verify that it can handle many classical protocol mismatch
    problems along with SoC problems. The initial idea for ACTL-based
    convertibility verification was presented at SLA++P ’07 as presented
    in the work by Roopak Sinha et al. 2008.
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