Result 1 to 20 of 41 total
Reducing test application time, test data volume and test power through Virtual Chain Partition. (English)
Integr., VLSI J. 42, No. 3, 385-399 (2009).
1
Testable design of AND-EXOR logic networks with universal test sets. (English)
Comput. Electr. Eng. 35, No. 5, 644-658 (2009).
2
Design-for-testability features and test implementation of a giga hertz general purpose microprocessor. (English)
J. Comput. Sci. Technol. 23, No. 6, 1037-1046 (2008).
3
Survey of software design for testability. (Chinese)
J. Comput. Appl. 28, No. 11, 2915-2918 (2008).
4
Testability analysis and improvements of register-transfer level digital circuits. (English)
Comput. Inform. 25, No. 5, 441-464 (2006).
5
InTeRail: A Test Architecture for Core-Based SOCs. (English)
IEEE Transactions on Computers 55, No.02, 137-149 (2006).
6
New beginnings, continued success. (English)
IEEE Design and Test of Computers 23, No.01, 5-6 (2006).
7
On Non-standard fault models for logic digital circuits: simulation, design for testability, industrial applications. (English)
it Inf. Technol. 47, No. 3, 172 (2005).
8
A new technique for $I_{DDQ}$ testing in nanometer technologies. (English)
Integr., VLSI J. 31, No.2, 183-194 (2002).
9
Scheduling and variable binding for improved testability in high level synthesis. (English)
Comput. Electr. Eng. 24, No. 5, 441-461 (1998).
10
Design of mixed-signal systems for testability. (English)
Integr., VLSI J. 26, No.1-2, 141-150 (1998).
11
High-level test synthesis: a survey. (English)
Integr., VLSI J. 26, No.1-2, 79-99 (1998).
12
Assignment and allocation of highly testable data paths under scan optimization. (English)
Integr., VLSI J. 21, No.3, 191-207 (1996).
13
Manifestations of faults in single- and double-BJT bicmos logic gates. (English)
IEE Proc., Comput. Digit. Tech. 142, No. 2, 135-144 (1995).
14
Testing differential split-level CMOS circuits. (English)
IEE Proc., Circuits Devices Syst. 141, No. 6, 451-456 (1994).
15
On GID-testable two-dimensional iterative arrays. (English)
J. Comput. Sci. Technol. 9, No.1, 27-36 (1994).
16
Optimal Configuring of Multiple Scan Chains. (English)
IEEE Transactions on Computers 42, No.09, 1121-1131 (1993).
17
Design of Pseudoexhaustive Testable PLA with Low Overhead. (English)
IEEE Transactions on Computers 42, No.07, 887-891 (1993).
18
Logic design theory. (English)
Prentice-Hall International Editions. Englewood Cliffs, NJ: Prentice Hall. xiii, 306 p. (1993).
19
FOCUS: An Experimental Environment for Fault Sensitivity Analysis. (English)
IEEE Transactions on Computers 41, No.12, 1515-1526 (1992).
20
Result 1 to 20 of 41 total
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