Result 1 to 20 of 36 total
Embedded-TM: energy and complexity-effective hardware transactional memory for embedded multicore systems. (English)
J. Parallel Distrib. Comput. 70, No. 10, 1042-1052 (2010).
1
Time space tradeoffs in GA based feature selection for workload characterization. (English)
García-Pedrajas, Nicolás (ed.) et al., Trends in applied intelligent systems. 23rd international conference on industrial engineering and other applications of applied intelligent systems, IEA/AIE 2010, Cordoba, Spain, June 1‒4, 2010. Proceedings, Part II. Berlin: Springer (ISBN 978-3-642-13024-3/pbk). Lecture Notes in Computer Science 6097. Lecture Notes in Artificial Intelligence, 643-652 (2010).
2
Power-efficient system design. (English)
New York, NY: Springer (ISBN 978-1-4419-6387-1/hbk; 978-1-4419-6388-8/ebook). x, 253~p. EUR~99.95/net; SFR~165.00 (2010).
3
L1 collective cache: Managing shared data for chip multiprocessors. (English)
Dou, Yong (ed.) et al., Advanced parallel processing technologies. 8th international symposium, APPT 2009, Rapperswil, Switzerland, August 24‒25, 2009. Proceedings. Berlin: Springer (ISBN 978-3-642-03643-9/pbk). Lecture Notes in Computer Science 5737, 123-133 (2009).
4
The design and evaluation of a selective way based trace cache. (English)
Dou, Yong (ed.) et al., Advanced parallel processing technologies. 8th international symposium, APPT 2009, Rapperswil, Switzerland, August 24‒25, 2009. Proceedings. Berlin: Springer (ISBN 978-3-642-03643-9/pbk). Lecture Notes in Computer Science 5737, 95-109 (2009).
5
Instruction hints for super efficient data caches. (English)
Allen, Gabrielle (ed.) et al., Computational science ‒ ICCS 2009. 9th international conference Baton Rouge, LA, USA, May 25‒27, 2009. Proceedings, Part II. Berlin: Springer (ISBN 978-3-642-01972-2/pbk). Lecture Notes in Computer Science 5545, 677-685 (2009).
6
CASA: A new IFU architecture for power-efficient instruction cache and TLB designs. (English)
J. Comput. Sci. Technol. 23, No. 1, 141-153 (2008).
7
Benefit-based data caching in ad hoc networks. (English)
IEEE Transactions on Mobile Computing 07, No. 03, 289-304 (2008).
8
On-demand solution to minimize i-cache leakage energy with maintaining performance. (English)
IEEE Trans. Comput. 57, No. 01, 7-24 (2008).
9
Architecting efficient interconnects for large caches with CACTI 6.0. (English)
IEEE Micro 28, No. 01, 69-79 (2008).
10
Dynamic predication of indirect jumps. (English)
IEEE Computer Architecture Letters 07, No. 01, 1-4 (2008).
11
Miss rate prediction across program inputs and cache configurations. (English)
IEEE Trans. Comput. 56, No. 03, 328-343 (2007).
12
Explaining dynamic cache partitioning speed ups. (English)
IEEE Computer Architecture Letters 06, No. 01 (2007).
13
Probabilistic prediction of temporal locality. (English)
IEEE Computer Architecture Letters 06, No. 01 (2007).
14
Nahalal: Cache organization for chip multiprocessors. (English)
IEEE Computer Architecture Letters 06, No. 01 (2007).
15
Constraint-aware large-scale CMP cache design. (English)
Aluru, Srinivas (ed.) et al., High performance computing ‒ HiPC 2007. 14th international conference, Goa, India, December 18‒21, 2007. Proceedings. Berlin: Springer (ISBN 978-3-540-77219-4/pbk). Lecture Notes in Computer Science 4873, 161-171 (2007).
16
Cache placement in sensor networks under an update cost constraint. (English)
J. Discrete Algorithms 5, No. 3, 422-435 (2007).
17
Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology. (English)
J. Comput. Sci. Technol. 22, No. 1, 1-14 (2007).
18
Instruction buffering exploration for low energy embedded processors. (English)
J. Embed. Comput. 1, No. 3, 341-351 (2005).
19
Bridging the Processor-Memory Performance Gapwith 3D IC Technology. (English)
IEEE Design and Test of Computers 22, No.06, 556-564 (2005).
20
Result 1 to 20 of 36 total
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