Result 1 to 20 of 105 total
Parsimonious circuits for error-tolerant applications through probabilistic logic minimization. (English)
Ayala, José L. (ed.) et al., Integrated circuit and system design. Power and timing modeling, optimization, and simulation. 21st international workshop, PATMOS 2011, Madrid, Spain, September 26‒29, 2011. Proceedings. Berlin: Springer (ISBN 978-3-642-24153-6/pbk). Lecture Notes in Computer Science 6951, 204-213 (2011).
1
Optimized design of parallel carry-select adders. (English)
Integr., VLSI J. 44, No. 1, 62-74 (2011).
2
Novel quantum compressor designs using new genetic algorithm-based simulator, analyzer and synthesizer software in nanotechnology. (English)
Int. J. Quantum Inf. 8, No. 7, 1219-1231 (2010).
3
Constant addition with flagged binary adder architectures. (English)
Integr., VLSI J. 43, No. 3, 258-267 (2010).
4
Formal proof of prefix adders. (English)
Math. Comput. Modelling 52, No. 1-2, 191-199 (2010).
5
On implementing efficient modulo $2^{n} + 1$ arithmetic components. (English)
J. Circuits Syst. Comput. 19, No. 5, 911-930 (2010).
6
Efficient modulo $2^n+1$ adder architectures. (English)
Integr., VLSI J. 42, No. 2, 149-157 (2009).
7
Parallelization of reversible ripple-carry adders. (English)
Parallel Process. Lett. 19, No. 2, 205-222 (2009).
8
Efficient reversible logic design of BCD subtractors. (English)
Gavrilova, Marina L. (ed.) et al., Transactions on Computational Science III. Berlin: Springer (ISBN 978-3-642-00211-3/pbk). Lecture Notes in Computer Science 5300. Journal Subline, 99-121 (2009).
9
Parallel optimization of a reversible (quantum) ripple-carry adder. (English)
Calude, Cristian S. (ed.) et al., Unconventional computation. 7th international conference, UC 2008, Vienna, Austria, August 25‒28, 2008. Proceedings. Berlin: Springer (ISBN 978-3-540-85193-6/pbk). Lecture Notes in Computer Science 5204, 228-241 (2008).
10
Negative save sign extension for multi-term adders and multipliers. (English)
J. VLSI Signal Process. 52, No. 1, 1-11 (2007).
11
New and improved architectures for Montgomery modular multiplication. (English)
Mob. Netw. Appl. 12, No. 4, 281-291 (2007).
12
Fast parallel-prefix architectures for modulo 2n-1 addition with a single representation of zero. (English)
IEEE Trans. Comput. 56, No. 11, 1484-1492 (2007).
13
Multioperand parallel decimal adder: A mixed binary and BCD approach. (English)
IEEE Trans. Comput. 56, No. 10, 1320-1328 (2007).
14
Design of multiple-valued arithmetic circuits using counter tree diagrams. (English)
J. Mult.-Val. Log. Soft Comput. 13, No. 4-6, 487-502 (2007).
15
Efficient hardware implementation of finite fields with applications to cryptography. (English)
Acta Appl. Math. 93, No. 1-3, 75-118 (2006).
16
On the design of efficient modular adders. (English)
J. Circuits Syst. Comput. 14, No. 5, 965-972 (2005).
17
Reviewing $4-to-2$ adders for multi-operand addition. (English)
J. VLSI Signal Process. 40, No. 1, 143-152 (2005).
18
Efficient reconfigurable Manchester adders for low-power media processing. (English)
J. Circuits Syst. Comput. 14, No. 1, 57-63 (2005).
19
Pipelined area-efficient digit serial divider. (English)
Signal Process. 83, No. 9, 2011-2020 (2003).
20
Result 1 to 20 of 105 total
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