Result 1 to 20 of 2059 total
VLSI analog filters. Active RC, OTA-C, and SC. (English)
Modeling and Simulation in Science, Engineering and Technology. Boston, MA: Birkhäuser (ISBN 978-0-8176-8357-3/hbk; 978-0-8176-8358-0/ebook). xvii, 620~p. EUR~99.95/net; SFR~127.50; \sterling~86.50/hbk (2013).
1
Simple wriggling is hard unless you are a fat hippo. (English)
Theory Comput. Syst. 50, No. 1, 93-110 (2012).
2
VLSI architecture for spatial domain spread spectrum image watermarking using gray-scale watermark. (English)
Rahaman, Hafizur (ed.) et al., Progress in VLSI design and test. 16th international symposium, VDAT 2012, Shibpur, India, July 1‒4, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-31493-3/pbk). Lecture Notes in Computer Science 7373, 375-376 (2012).
3
A faster hierarchical balanced bipartitioner for VLSI floorplans using monotone staircase cuts. (English)
Rahaman, Hafizur (ed.) et al., Progress in VLSI design and test. 16th international symposium, VDAT 2012, Shibpur, India, July 1‒4, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-31493-3/pbk). Lecture Notes in Computer Science 7373, 327-336 (2012).
4
Delay uncertainty in single- and multi-wall carbon nanotube interconnects. (English)
Rahaman, Hafizur (ed.) et al., Progress in VLSI design and test. 16th international symposium, VDAT 2012, Shibpur, India, July 1‒4, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-31493-3/pbk). Lecture Notes in Computer Science 7373, 289-299 (2012).
5
Arithmetic algorithms for ternary number system. (English)
Rahaman, Hafizur (ed.) et al., Progress in VLSI design and test. 16th international symposium, VDAT 2012, Shibpur, India, July 1‒4, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-31493-3/pbk). Lecture Notes in Computer Science 7373, 111-120 (2012).
6
Reducing the multiplier-complexity of massively parallel polyphase 2D IIR broadband beam filters. (English)
Circuits Syst. Signal Process. 31, No. 3, 1229-1243 (2012).
7
Global routing in VLSI design: algorithms, theory, and computational practice. (English)
J. Comb. Math. Comb. Comput. 80, 71-93 (2012).
8
Design and comparison of FFT VLSI architectures for SoC telecom applications with different flexibility, speed and complexity trade-offs. (English)
Circuits Syst. Signal Process. 31, No. 2, 627-649 (2012).
9
Effects of quantization in systolic 2D IIR beam filters on UWB wireless communications. (English)
Circuits Syst. Signal Process. 31, No. 2, 595-610 (2012).
10
Reconciling fault-tolerant distributed computing and systems-on-chip. (English)
Distrib. Comput. 24, No. 6, 323-355 (2012).
11
The complexity of VLSI power-delay optimization by interconnect resizing. (English)
J. Comb. Optim. 23, No. 2, 292-300 (2012).
12
Using well-solvable quadratic assignment problems for VLSI interconnect applications. (English)
Discrete Appl. Math. 160, No. 4-5, 525-535 (2012).
13
Dynamics of VLSI analog decoupled neurons. (English)
Neurocomputing 82, 234-237 (2012).
14
A new scheme of test data compression based on equal-run-length coding (ERLC). (English)
Integr., VLSI J. 45, No. 1, 91-98 (2012).
15
Design of multi-mode application-specific cores based on high-level synthesis. (English)
Integr., VLSI J. 45, No. 1, 9-21 (2012).
16
VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000. (English)
Integr., VLSI J. 45, No. 1, 1-8 (2012).
17
Architecture design of high-efficient and non-memory AES crypto-core for WPAN. (English)
Concurrency Comput. Pract. Exp. 23, No. 12, 1332-1347 (2011).
18
A survey of VLSI circuit partitioning algorithms. (Chinese)
J. Fuzhou Univ., Nat. Sci. 39, No. 5, 622-630 (2011).
19
VLSI floorplanning based on a hybrid differential evolution algorithm. (Chinese)
J. Fuzhou Univ., Nat. Sci. 39, No. 4, 497-502 (2011).
20
Result 1 to 20 of 2059 total
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