Result 1 to 20 of 276 total
Low power multiple-value voltage-mode look-up table for quaternary field programmable gate arrays. (English)
J. Low Power Electron. 7, No. 2, 294-301 (2011).
1
Optimal logic architecture and supply voltage selection method to reduce the impact of the threshold voltage variation on the timing. (English)
J. Low Power Electron. 7, No. 2, 285-293 (2011).
2
Self-timed SRAM for energy harvesting systems. (English)
J. Low Power Electron. 7, No. 2, 274-284 (2011).
3
On-line power optimization of data flow multi-core architecture based on vdd-hopping for local dynamic voltage and frequency scaling. (English)
J. Low Power Electron. 7, No. 2, 265-273 (2011).
4
An automated power emulation framework for embedded software - detecting power-critical code regions and optimizing software-induced power consumption peaks. (English)
J. Low Power Electron. 7, No. 2, 255-264 (2011).
5
Selected articles from the PATMOS 2010 workshop. (English)
J. Low Power Electron. 7, No. 2, 254 (2011).
6
Transparent-segmented-scan without the routing overhead of segmented-scan. (English)
J. Low Power Electron. 7, No. 2, 245-253 (2011).
7
Spintronic memristor: compact model and statistical analysis. (English)
J. Low Power Electron. 7, No. 2, 234-244 (2011).
8
Digital sliding mode control of DC-DC buck converters. (English)
J. Low Power Electron. 7, No. 2, 218-233 (2011).
9
Evaluation of parasitic components in LC oscillators by time-varying root-locus. (English)
J. Low Power Electron. 7, No. 2, 209-217 (2011).
10
An optimum body biasing for gain and linearity control in CMOS low-noise amplifiers. (English)
J. Low Power Electron. 7, No. 2, 199-208 (2011).
11
Lower $V_{DD}$ operation of FPGA-based digital circuits through delay modeling and time borrowing. (English)
J. Low Power Electron. 7, No. 2, 185-198 (2011).
12
Hybrid subthreshold and nearthreshold design methodology for energy minimization. (English)
J. Low Power Electron. 7, No. 2, 172-184 (2011).
13
Process variation tolerant finfet based robust low power SRAM cell design at 32 nm technology. (English)
J. Low Power Electron. 7, No. 2, 163-171 (2011).
14
Power-gated arithmetic circuits for energy-precision tradeoffs in mobile graphics processing units. (English)
J. Low Power Electron. 7, No. 2, 148-162 (2011).
15
Instruction-based voltage scaling for power reduction in SIMD mpsocs. (English)
J. Low Power Electron. 7, No. 2, 141-147 (2011).
16
Resource management in heterogeneous wireless sensor networks. (English)
J. Low Power Electron. 7, No. 2, 123-140 (2011).
17
Cyber-physical thermal management of 3D multi-core cache-processor system with microfluidic cooling. (English)
J. Low Power Electron. 7, No. 1, 110-121 (2011).
18
A bit-interleaved 2-port subthreshold 6T SRAM array with high write-ability and SNM-free read in 90 nm. (English)
J. Low Power Electron. 7, No. 1, 96-109 (2011).
19
Oxide-tunneling leakage suppressed SRAM for sub-65-nm very large scale integrated circuits. (English)
J. Low Power Electron. 7, No. 1, 87-95 (2011).
20
Result 1 to 20 of 276 total
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