Result 1 to 20 of 136 total
Evaluating indirect branch handling mechanisms in software dynamic translation systems. (English)
ACM Trans. Archit. Code Optim. 8, No. 2, 9 (2011).
1
Deft: design space exploration for on-the-fly detection of coherence misses. (English)
ACM Trans. Archit. Code Optim. 8, No. 2, 8 (2011).
2
Efficient and effective misaligned data access handling in a dynamic binary translation system. (English)
ACM Trans. Archit. Code Optim. 8, No. 2, 7 (2011).
3
Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. (English)
ACM Trans. Archit. Code Optim. 8, No. 2, 6 (2011).
4
Parallelization libraries: characterizing and reducing overheads. (English)
ACM Trans. Archit. Code Optim. 8, No. 1, 5 (2011).
5
Deterministic finite automata characterization and optimization for scalable pattern matching. (English)
ACM Trans. Archit. Code Optim. 8, No. 1, 4 (2011).
6
Adaptive timekeeping replacement: fine-grained capacity management for shared CMP caches. (English)
ACM Trans. Archit. Code Optim. 8, No. 1, 3 (2011).
7
Exploring the effects of on-chip thermal variation on high-performance multicore architectures. (English)
ACM Trans. Archit. Code Optim. 8, No. 1, 2 (2011).
8
Fine-grained DVFS using on-chip regulators. (English)
ACM Trans. Archit. Code Optim. 8, No. 1, 1 (2011).
9
Understanding the behavior and implications of context switch misses. (English)
ACM Trans. Archit. Code Optim. 7, No. 4, 21 (2010).
10
Collective optimization: A practical collaborative approach. (English)
ACM Trans. Archit. Code Optim. 7, No. 4, 20 (2010).
11
Federation: boosting per-thread performance of throughput-oriented manycore architectures. (English)
ACM Trans. Archit. Code Optim. 7, No. 4, 19 (2010).
12
Disirer: converting a retargetable compiler into a multiplatform binary translator. (English)
ACM Trans. Archit. Code Optim. 7, No. 4, 18 (2010).
13
Impact of high-level transformations within the ROCCC framework. (English)
ACM Trans. Archit. Code Optim. 7, No. 4, 17 (2010).
14
Exploiting compression opportunities to improve spmxv performance on shared memory systems. (English)
ACM Trans. Archit. Code Optim. 7, No. 3, 16 (2010).
15
Design exploration of hybrid caches with disparate memory technologies. (English)
ACM Trans. Archit. Code Optim. 7, No. 3, 15 (2010).
16
Quality of service shared cache management in chip multiprocessor architecture. (English)
ACM Trans. Archit. Code Optim. 7, No. 3, 14 (2010).
17
Pipa: pipelined profiling and analysis on multicore systems. (English)
ACM Trans. Archit. Code Optim. 7, No. 3, 13 (2010).
18
Performance-aware thermal management via task scheduling. (English)
ACM Trans. Archit. Code Optim. 7, No. 1 (2010).
19
A hardware/software framework for instruction and data scratchpad memory allocation. (English)
ACM Trans. Archit. Code Optim. 7, No. 1 (2010).
20
Result 1 to 20 of 136 total