io-port.net

io-port 05928137 Mukherjee, Nilanjan; Pogiel, Artur; Rajski, Janusz; Tyszer, Jerzy

BIST-based fault diagnosis for read-only memories. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 7, 1072-1085 (2011).

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io-port 05928136 Lin, Yen-Tzu; D. (Shawn) Blanton, R.

METER: measuring test effectiveness regionally. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 7, 1058-1071 (2011).

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io-port 05928135 Chou, Sheng; Han, Cheng-Shen; Huang, Po-Kai; Tien, Ko-Fan; Ho, Tsung-Yi

An effective and efficient framework for clock latency range aware clock network synthesis. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 7, 1045-1057 (2011).

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io-port 05928134 Lin, Jai-Ming; Hung, Zhi-Xiong

UFO: unified convex optimization algorithms for fixed-outline floorplanning considering pre-placed modules. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 7, 1034-1044 (2011).

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io-port 05928133 Yan, Jackey Z.; Chu, Chris C.N.; Mak, Wai-Kei

Safechoice: A novel approach to hypergraph clustering for wirelength-driven placement. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 7, 1020-1033 (2011).

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io-port 05928132 Rubanov, Nikolay

A general framework to perform the Max/MIN operations in parameterized statistical timing analysis using information theoretic concepts. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 7, 1011-1019 (2011).

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io-port 05928131 Xiao, Zigang; Young, Evangeline F.Y.

Placement and routing for cross-referencing digital microfluidic biochips. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 7, 1000-1010 (2011).

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io-port 05928130 Zhao, Yang; Xu, Tao; Chakrabarty, Krishnendu

Broadcast electrode-addressing and scheduling methods for pin-constrained digital microfluidic biochips. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 7, 986-999 (2011).

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io-port 05928129 Suvak, Onder; Demir, Alper

On phase models for oscillators. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 7, 972-985 (2011).

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io-port 05928128 Brambilla, Angelo; Gruosso, Giambattista; Gajani, Giancarlo Storti

A probe-based harmonic balance method to simulate coupled oscillators. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 7, 960-971 (2011).

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io-port 05928126 Rivers, Jude A.; Gupta, Meeta Sharma; Shin, Jeonghee; Kudva, Prabhakar; Bose, Pradip

Error tolerance in server class processors. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 7, 945-959 (2011).

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io-port 05922005 Cong, J.; Huang, H.; Jiang, W.

Pattern-mining for behavioral synthesis. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 6, 939-944 (2011).

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io-port 05922004 Tannir, Dani; Khazaka, Roni

Adjoint sensitivity analysis of nonlinear distortion in radio frequency circuits. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 6, 934-939 (2011).

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io-port 05922003 Hsieh, T.-Y.; Lee, K.-J.; Breuer, M.A.

An error-tolerance-based test methodology to support product grading for yield enhancement. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 6, 930-934 (2011).

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io-port 05922002 Lee, M.; Denq, L.-M.; Wu, C.-W.

A memory built-in self-repair scheme based on configurable spares. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 6, 919-929 (2011).

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io-port 05922001 Kang, K.; Kim, J.; Yoo, S.; Kyung, C.-M.

Runtime power management of 3-D multi-core architectures under peak power and temperature constraints. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 6, 905-918 (2011).

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io-port 05922000 Drego, N.; Chandrakasan, A.; Boning, D.; Shah, D.

Reduction of variation-induced energy overhead in multi-core processors. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 6, 891-904 (2011).

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io-port 05921999 Rajaram, A.; Pan, D.Z.

Robust chip-level clock tree synthesis. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 6, 877-890 (2011).

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io-port 05921998 Chen, Q.; Schoenmaker, Wim; Meuris, Peter; Wong, N.

An effective formulation of coupled electromagnetic-TCAD simulation for extremely high frequency onward. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 6, 866-876 (2011).

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io-port 05921997 Veetil, Vineeth; Chopra, Kaviraj; Blaauw, David; Sylvester, Dennis

Fast statistical static timing analysis using smart Monte Carlo techniques. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 6, 852-865 (2011).

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