Result 1 to 20 of 383 total
Electromagnetic interference suppression techniques for compact LED lamp drivers. (English)
J. Circuits Syst. Comput. 19, No. 5, 1131-1139 (2010).
1
A compact memory-free architecture for the AES algorithm using resource sharing methods. (English)
J. Circuits Syst. Comput. 19, No. 5, 1109-1130 (2010).
2
High performance scalable mixed-radix-$2^{n}$ serial-serial multipliers for GF$(2^{m})$. (English)
J. Circuits Syst. Comput. 19, No. 5, 1089-1107 (2010).
3
A novel adaptive current biased linear radio-frequency power amplifier on sige HBT process. (English)
J. Circuits Syst. Comput. 19, No. 5, 1077-1088 (2010).
4
New realizations of voltage-mode quadrature oscillators using current differencing buffered amplifiers. (English)
J. Circuits Syst. Comput. 19, No. 5, 1069-1076 (2010).
5
Choosing between design options for real-time computers tolerating a single fault. (English)
J. Circuits Syst. Comput. 19, No. 5, 1041-1068 (2010).
6
Complex CMOS gate collapsing technique and its application to transient time. (English)
J. Circuits Syst. Comput. 19, No. 5, 1025-1040 (2010).
7
Realization of square root domain Tow - Thomas biquadratic filter. (English)
J. Circuits Syst. Comput. 19, No. 5, 1015-1024 (2010).
8
Novel FCS-based layout-friendly accurate wide-band low-power CCII- realizations. (English)
J. Circuits Syst. Comput. 19, No. 5, 997-1014 (2010).
9
Evaluation framework for K-best sphere decoders. (English)
J. Circuits Syst. Comput. 19, No. 5, 975-995 (2010).
10
Early buffer planning with congestion control using buffer requirement map. (English)
J. Circuits Syst. Comput. 19, No. 5, 949-973 (2010).
11
On the new design of sinusoid voltage controlled oscillators using multiplier in CFA-based double integrator loop. (English)
J. Circuits Syst. Comput. 19, No. 5, 939-948 (2010).
12
Implementation of an RF CMOS quadrature LC voltage-controlled oscillator based on the switched tail transistor topology. (English)
J. Circuits Syst. Comput. 19, No. 5, 931-937 (2010).
13
On implementing efficient modulo $2^{n} + 1$ arithmetic components. (English)
J. Circuits Syst. Comput. 19, No. 5, 911-930 (2010).
14
Statistical testing of a chaos based CMOS true-random number generator. (English)
J. Circuits Syst. Comput. 19, No. 4, 897-910 (2010).
15
A variability-tolerant feedback technique for throughput maximization of TRBGs with predefined entropy. (English)
J. Circuits Syst. Comput. 19, No. 4, 879-895 (2010).
16
A non-conservative model of second-order RC sinusoidal oscillators. (English)
J. Circuits Syst. Comput. 19, No. 4, 871-877 (2010).
17
Higher-order chaotic oscillator using active Bessel filter. (English)
J. Circuits Syst. Comput. 19, No. 4, 859-869 (2010).
18
A low-voltage scalable (1.8 V - 0.75 V) CMOS folded-cascode LC quadrature VCO for RF receivers. (English)
J. Circuits Syst. Comput. 19, No. 4, 835-857 (2010).
19
Complex pattern in a ring of van der Pol oscillators coupled by time-varying resistors. (English)
J. Circuits Syst. Comput. 19, No. 4, 819-834 (2010).
20
Result 1 to 20 of 383 total
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