Result 41 to 60 of 328 total
Optimized high-order finite difference wave equations modeling on reconfigurable computing platform. (English)
Microprocess. Microsyst. 31, No. 2, 103-115 (2007).
41
Special issue with selected papers from the 11th IEEE symposium on computers and communications (ISCC’06). (English)
Microprocess. Microsyst. 31, No. 4, 213-214 (2007).
42
An automated, FPGA-based reconfigurable, low-power RFID tag. (English)
Microprocess. Microsyst. 31, No. 2, 116-134 (2007).
43
A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor. (English)
Microprocess. Microsyst. 31, No. 2, 146-159 (2007).
44
Reconfigurable system for high-speed and diversified AES using FPGA. (English)
Microprocess. Microsyst. 31, No. 2, 94-102 (2007).
45
Accelerating sequential programs on chip multiprocessors via dynamic prefetching thread. (English)
Microprocess. Microsyst. 31, No. 3, 200-211 (2007).
46
System on chips optimization using ABV and automatic generation of systemc codes. (English)
Microprocess. Microsyst. 31, No. 7, 433-444 (2007).
47
A reconfigurable computing framework for multi-scale cellular image processing. (English)
Microprocess. Microsyst. 31, No. 8, 546-563 (2007).
48
Multiplierless and fully pipelined JPEG compression soft IP targeting fpgas. (English)
Microprocess. Microsyst. 31, No. 8, 487-497 (2007).
49
Executing large algorithms on low-capacity fpgas using flowpath partitioning and runtime reconfiguration. (English)
Microprocess. Microsyst. 31, No. 5, 302-312 (2007).
50
Indoor solar energy harvesting for sensor network router nodes. (English)
Microprocess. Microsyst. 31, No. 6, 420-432 (2007).
51
Reconfigurable computing system for image processing via the internet. (English)
Microprocess. Microsyst. 31, No. 8, 498-515 (2007).
52
Special issue on sensor systems. (English)
Microprocess. Microsyst. 31, No. 6, 369 (2007).
53
Design optimization and space minimization considering timing and code size via retiming and unfolding. (English)
Microprocess. Microsyst. 30, No. 4, 173-183 (2006).
54
A selective DVS technique based on battery residual. (English)
Microprocess. Microsyst. 30, No. 1, 33-42 (2006).
55
Maximum sequence test pattern generators with irreducible characteristic polynomials. (English)
Microprocess. Microsyst. 30, No. 2, 117-123 (2006).
56
A parallel algorithm, architecture and FPGA realization for high speed determination of the complete visibility graph for convex objects. (English)
Microprocess. Microsyst. 30, No. 1, 1-14 (2006).
57
Application-specific SIMD synthesis for reconfigurable architectures. (English)
Microprocess. Microsyst. 30, No. 6, 398-412 (2006).
58
Transform decomposition method of pruning the FHT algorithms. (English)
Microprocess. Microsyst. 30, No. 4, 184-188 (2006).
59
Rapid generation of custom instructions using predefined dataflow structures. (English)
Microprocess. Microsyst. 30, No. 6, 355-366 (2006).
60
Result 41 to 60 of 328 total
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