Result 41 to 60 of 342 total
Exploration of distributed shared memory architectures for noc-based multiprocessors. (English)
J. Syst. Archit. 53, No. 10, 719-732 (2007).
41
A multi-channel architecture for high-performance NAND flash-based storage system. (English)
J. Syst. Archit. 53, No. 9, 644-658 (2007).
42
Energy consumption analysis for two embedded Java virtual machines. (English)
J. Syst. Archit. 53, No. 5-6, 328-337 (2007).
43
Efficient segment-based video transcoding proxy for mobile multimedia services. (English)
J. Syst. Archit. 53, No. 11, 833-845 (2007).
44
Test data compression scheme based on variable-to-fixed-plus-variable-length coding. (English)
J. Syst. Archit. 53, No. 11, 877-887 (2007).
45
Design space exploration of reliable networked embedded systems. (English)
J. Syst. Archit. 53, No. 10, 751-763 (2007).
46
Simulated and measured performance evaluation of RISC-based soc platforms in network processing applications. (English)
J. Syst. Archit. 53, No. 10, 703-718 (2007).
47
Speculative trivialization point advancing in high-performance processors. (English)
J. Syst. Archit. 53, No. 9, 587-601 (2007).
48
Editorial. (English)
J. Syst. Archit. 53, No. 8, 465 (2007).
49
Low power data processing system with self-reconfigurable architecture. (English)
J. Syst. Archit. 53, No. 9, 568-576 (2007).
50
Resource efficiency of the giganetic chip multiprocessor architecture. (English)
J. Syst. Archit. 53, No. 5-6, 285-299 (2007).
51
Quantum ternary parallel adder/subtractor with partially-look-ahead carry. (English)
J. Syst. Archit. 53, No. 7, 453-464 (2007).
52
Effectiveness of caching in a distributed digital library system. (English)
J. Syst. Archit. 53, No. 7, 403-416 (2007).
53
Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures. (English)
J. Syst. Archit. 53, No. 10, 689-702 (2007).
54
Editorial. (English)
J. Syst. Archit. 53, No. 5-6, 251-252 (2007).
55
High-speed hardware implementations of elliptic curve cryptography: A survey. (English)
J. Syst. Archit. 53, No. 2-3, 72-84 (2007).
56
Hardware support for adaptive tessellation of bézier surfaces based on local tests. (English)
J. Syst. Archit. 53, No. 4, 233-250 (2007).
57
The segbus platform - architecture and communication mechanisms. (English)
J. Syst. Archit. 53, No. 4, 151-169 (2007).
58
A comparison of two policies for issuing instructions speculatively. (English)
J. Syst. Archit. 53, No. 4, 170-183 (2007).
59
Fast hardware for modular exponentiation with efficient exponent pre-processing. (English)
J. Syst. Archit. 53, No. 2-3, 99-108 (2007).
60
Result 41 to 60 of 342 total