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Feasibility of decoupling memory management from the execution pipeline. (English)
J. Syst. Archit. 53, No. 12, 927-936 (2007).
WorldCat.org
1
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STAFF: A flash driver algorithm minimizing block erasures. (English)
J. Syst. Archit. 53, No. 12, 889-901 (2007).
WorldCat.org
2
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Dual actuator logging disk architecture and modeling. (English)
J. Syst. Archit. 53, No. 12, 913-926 (2007).
WorldCat.org
3
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Enhanced fault tolerant routing algorithms using a concept of "balanced ring". (English)
J. Syst. Archit. 53, No. 12, 902-912 (2007).
WorldCat.org
4
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A platform-based soc design and implementation of scalable automaton matching for deep packet inspection. (English)
J. Syst. Archit. 53, No. 12, 937-950 (2007).
WorldCat.org
5
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Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms. (English)
J. Syst. Archit. 53, No. 8, 511-523 (2007).
WorldCat.org
6
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Achieving multipoint-to-multipoint fairness with RCNWA. (English)
J. Syst. Archit. 53, No. 7, 437-452 (2007).
WorldCat.org
7
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Chip size estimation for SOC design space exploration. (English)
J. Syst. Archit. 53, No. 10, 764-776 (2007).
WorldCat.org
8
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A system architecture for high-speed deep packet inspection in signature-based network intrusion prevention. (English)
J. Syst. Archit. 53, No. 5-6, 310-320 (2007).
WorldCat.org
9
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A heuristic fault-tolerant routing algorithm in mesh using rectilinear-monotone polygonal fault blocks. (English)
J. Syst. Archit. 53, No. 9, 619-628 (2007).
WorldCat.org
10
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Efficient FPGA implementation of DWT and modified SPIHT for lossless image compression. (English)
J. Syst. Archit. 53, No. 7, 369-378 (2007).
WorldCat.org
11
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Accumulator-based pseudo-exhaustive two-pattern generation. (English)
J. Syst. Archit. 53, No. 11, 846-860 (2007).
WorldCat.org
12
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A low-cost strategy to provide full QoS support in advanced switching networks. (English)
J. Syst. Archit. 53, No. 7, 355-368 (2007).
WorldCat.org
13
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Multiprogrammed non-blocking checkpoints in support of optimistic simulation on myrinet clusters. (English)
J. Syst. Archit. 53, No. 9, 659-676 (2007).
WorldCat.org
14
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Automated memory-aware application distribution for multi-processor system-on-chips. (English)
J. Syst. Archit. 53, No. 11, 795-815 (2007).
WorldCat.org
15
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Benchmarking mesh and hierarchical bus networks in system-on-chip context. (English)
J. Syst. Archit. 53, No. 8, 477-488 (2007).
WorldCat.org
16
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Static scheduling techniques for dependent tasks on dynamically reconfigurable devices. (English)
J. Syst. Archit. 53, No. 11, 861-876 (2007).
WorldCat.org
17
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A new mixed radix conversion algorithm MRC-II. (English)
J. Syst. Archit. 53, No. 9, 577-586 (2007).
WorldCat.org
18
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Asynchronous arbiter for micro-threaded chip multiprocessors. (English)
J. Syst. Archit. 53, No. 5-6, 253-262 (2007).
WorldCat.org
19
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Tornado: A self-reconfiguration control system for core-based multiprocessor csopcs. (English)
J. Syst. Archit. 53, No. 9, 629-643 (2007).
WorldCat.org
20
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Result 1 to 20 of 342 total

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