Result 61 to 80 of 183 total
Watermarking graph partitioning solutions. (English)
Des. Autom. Embed. Syst. 9, No. 3, 211-227 (2005).
61
New alternatives to the estimation problem in hardware-software codesign of complex embedded systems: The H.261 video co-dec case study. (English)
Des. Autom. Embed. Syst. 9, No. 3, 193-210 (2005).
62
Temporal partitioning and scheduling data flow graphs for reconfigurable computers. (English)
Des. Autom. Embed. Syst. 9, No. 3, 177-191 (2005).
63
Survey and taxonomy of IP address lookup algorithms. (English)
Des. Autom. Embed. Syst. 9, No. 3, 163-176 (2005).
64
Scheduling for embedded real-time systems. (English)
Des. Autom. Embed. Syst. 9, No. 2, 141-154 (2005).
65
Adder based residue to binary number converters for $(2^{n+1}, 2^{n}, 2^{n-1})$. (English)
Des. Autom. Embed. Syst. 9, No. 2, 123-139 (2005).
66
Data and memory optimizations for embedded systems. (English)
Des. Autom. Embed. Syst. 9, No. 2, 101-121 (2005).
67
Formal methods reality check: Industrial usage. (English)
Des. Autom. Embed. Syst. 9, No. 2, 67-99 (2005).
68
Interfacing software libraries from nondeterministic prototypes. (English)
Des. Autom. Embed. Syst. 8, No. 4, 327-343 (2003).
69
Hybrid multi-FPGA board evaluation by permitting limited multi-hop routing. (English)
Des. Autom. Embed. Syst. 8, No. 4, 309-326 (2003).
70
Hardware-assisted signal activity analysis for power estimation in rapid prototyped systems. (English)
Des. Autom. Embed. Syst. 8, No. 4, 297-308 (2003).
71
On the rapid prototyping of equalizers for OFDM systems. (English)
Des. Autom. Embed. Syst. 8, No. 4, 283-295 (2003).
72
Towards automatic validation of dynamic behavior in pipelined processor specifications. (English)
Des. Autom. Embed. Syst. 8, No. 2-3, 249-265 (2003).
73
A remote methodology for embedded systems design and validation. (English)
Des. Autom. Embed. Syst. 8, No. 2-3, 229-247 (2003).
74
Fast and time-accurate cosimulation with OS scheduler modeling. (English)
Des. Autom. Embed. Syst. 8, No. 2-3, 211-228 (2003).
75
Performance analysis of arbitration policies for SoC communication architectures. (English)
Des. Autom. Embed. Syst. 8, No. 2-3, 189-210 (2003).
76
Enhanced symbolic simulation for functional verification of embedded array systems. (English)
Des. Autom. Embed. Syst. 8, No. 2-3, 173-188 (2003).
77
Towards SoC validation through prototyping: A systematic approach based on reconfigurable platform. (English)
Des. Autom. Embed. Syst. 8, No. 2-3, 155-171 (2003).
78
Formal verification for embedded system designs. (English)
Des. Autom. Embed. Syst. 8, No. 2-3, 139-153 (2003).
79
An efficient simulation environment and simulation techniques for Bluetooth device design. (English)
Des. Autom. Embed. Syst. 8, No. 2-3, 119-138 (2003).
80
Result 61 to 80 of 183 total