Result 1 to 11 of 11 total
Stress-aware module placement on reconfigurable devices (English)
FPL, 277-281 (2011).
1
Unifying partitioning and placement for SAT-based exploration of heterogeneous reconfigurable socs (English)
FPL, 429-434 (2011).
2
Symbolic design space exploration for multi-mode reconfigurable systems (English)
CODES+ISSS, 129-138 (2011).
3
Using the power side channel of fpgas for communication (English)
FCCM, 237-244 (2010).
4
Multiplexing methods for power watermarking (English)
HOST, 36-41 (2010).
5
A rapid prototyping system for error-resilient multi-processor systems-on-chip (English)
DATE, 375-380 (2010).
6
Concepts for autonomous control flow checking for embedded CPUs. (English)
Rong, Chunming (ed.) et al., Autonomic and trusted computing. 5th international conference, ATC 2008, Oslo, Norway, June 23‒25, 2008. Proceedings. Berlin: Springer (ISBN 978-3-540-69294-2/pbk). Lecture Notes in Computer Science 5060, 234-248 (2008).
7
Power signature watermarking of IP cores for fpgas (English)
Signal Processing Systems 51, No. 1, 123-136 (2008).
8
Concepts for autonomous control flow checking for embedded cpus (English)
ATC, 234-248 (2008).
9
Power signature watermarking of IP cores for fpgas. (English)
J. VLSI Signal Process. 51, No. 1, 123-136 (2007).
10
Identifying FPGA IP-cores based on lookup table content analysis (English)
FPL, 1-6 (2006).
11
Result 1 to 11 of 11 total
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