Result 1 to 20 of 36 total
Scan chain ordering to reduce test data for BIST-aided scan test using compatible scan flip-flops (English)
IEICE Transactions 93-D, No. 1, 10-16 (2010).
1
Test data reduction for BIST-aided scan test using compatible flip-flops and shifting inverter code (English)
Asian Test Symposium, 163-166 (2010).
2
Current-based testable design of level shifters in liquid crystal display drivers (English)
European Test Symposium, 262 (2010).
3
New class of tests for open faults with considering adjacent lines (English)
Asian Test Symposium, 301-306 (2009).
4
Fault effect of open faults considering adjacent signal lines in a 90 nm IC (English)
VLSI Design, 91-96 (2009).
5
A novel approach for improving the quality of open fault diagnosis (English)
VLSI Design, 85-90 (2009).
6
Test generation and diagnostic test generation for open faults with considering adjacent lines (English)
DFT, 243-251 (2007).
7
Current testable design of resistor string dacs (English)
DELTA, 197-200 (2006).
8
Reducing scan shifts using configurations of compatible and folding scan trees (English)
J. Electronic Testing 21, No. 6, 613-620 (2005).
9
Electric field for detecting open leads in CMOS logic circuits by supply current testing (English)
ISCAS (3), 2995-2998 (2005).
10
A test circuit for pin shorts generating oscillation in CMOS logic circuits. (English)
Syst. Comput. Jpn. 35, No. 13, 10-20 (2004).
11
Test sequence generation for test time reduction of IDDQ testing (English)
IEICE Transactions 87-D, No. 3, 537-543 (2004).
12
Identification and frequency estimation of feedback bridging faults generating logical oscillation in CMOS circuits (English)
IEICE Transactions 87-D, No. 3, 571-579 (2004).
13
On configuring scan trees to reduce scan shifts based on a circuit structure (English)
DELTA, 269-274 (2004).
14
Practical fault coverage of supply current tests for bipolar ics (English)
DELTA, 189-194 (2004).
15
A power supply circuit recycling charge in adiabatic dynamic CMOS logic circuits (English)
DELTA, 306-311 (2004).
16
CMOS open fault detection by appearance time of switching supply current (English)
DELTA, 183-188 (2004).
17
I\_DDQ test method based on wavelet transformation for noisy current measurement environment (English)
Asian Test Symposium, 112-117 (2004).
18
Reducing scan shifts using folding scan trees (English)
Asian Test Symposium, 6-11 (2003).
19
A BIST circuit for IDDQ tests (English)
Asian Test Symposium, 390-395 (2003).
20
Result 1 to 20 of 36 total
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