Result 1 to 10 of 10 total
A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of $4.45 \times 10^{-19}$ (English)
ESSCIRC, 527-530 (2011).
1
Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy (English)
CICC, 1-4 (2011).
2
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure (English)
IOLTS, 151-156 (2011).
3
Haptic canvas: dilatant fluid based haptic interaction (English)
SIGGRAPH Emerging Technologies (2010).
4
7T SRAM enabling low-energy simultaneous block copy (English)
CICC, 1-4 (2010).
5
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme (English)
ISQED, 659-663 (2009).
6
io-port 70556064 Matsumura, Yasushi;
Kuwata, Shigeki;
Yamamoto, Yuichiro;
Izumi, Kazunori;
Okada, Yasushi;
Hazumi, Michihiro;
Yoshimoto, Sachiko;
Mineno, Takahiro;
Nagahama, Munetoshi;
Fujii, Ayumi;
Takeda, Hiroshi
Template-based data entry for general description in medical records and data transfer to data warehouse for analysis (English)
MedInfo, 412-416 (2007).
7
Fingerprint identification using the accidental coincidence probability (English)
MVA, 124-127 (2002).
8
New adaptive Kalman filters using filter bank (English)
ISCAS (3), 49-52 (2002).
9
A new block adaptive algorithm using order recursive UD factorization method (English)
ISCAS, 369-372 (1994).
10
Result 1 to 10 of 10 total
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