Result 1 to 10 of 10 total
Test quality analysis and improvement for an embedded asynchronous FIFO (English)
DATE, 859-864 (2007).
1
Design and dft of a high-speed area-efficient embedded asynchronous FIFO (English)
DATE, 853-858 (2007).
2
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 24, No. 1, 4-17 (2005).
3
An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration (English)
DATE, 878-883 (2004).
4
Clock synchronization through handshake signalling. (English)
Microprocess. Microsyst. 27, No. 9, 447-460 (2003).
5
Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip (English)
DATE, 10350-10355 (2003).
6
Networks on silicon: blessing or nightmare? (English)
DSD, 196-200 (2002).
7
Clock synchronization through handshake signalling (English)
ASYNC, 59-68 (2002).
8
Networks on silicon: combining best-effort and guaranteed services (English)
DATE, 423-427 (2002).
9
Xetal: a low-power high-performance smart camera processor (English)
ISCAS (5), 215-218 (2001).
10
Result 1 to 10 of 10 total
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