Result 1 to 20 of 95 total
Parametric timing analysis and its application to dynamic voltage scaling. (English)
ACM Trans Embed. Comput. Syst. 10, No. 2, 25 (2010).
1
Improving both the performance benefits and speed of optimization phase sequence searches (English)
LCTES, 95-104 (2010).
2
Practical exhaustive optimization phase order exploration and evaluation. (English)
ACM Trans. Archit. Code Optim. 6, No. 1 (2009).
3
Introduction. (English)
Stenström, Per (ed.), Transactions on High-Performance Embedded Architectures and Compilers II. Berlin: Springer (ISBN 978-3-642-00903-7/pbk). Lecture Notes in Computer Science 5470. Journal Subline, 3 (2009).
4
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE) (English)
LCTES, 119-128 (2009).
6
io-port 05452412 Wilhelm, Reinhard;
Engblom, Jakob;
Ermedahl, Andreas;
Holsti, Niklas;
Thesing, Stephan;
Whalley, David B.;
Bernat, Guillem;
Ferdinand, Christian;
Heckmann, Reinhold;
Mitra, Tulika;
Mueller, Frank;
Puaut, Isabelle;
Puschner, Peter P.;
Staschulat, Jan;
Stenström, Per
The worst-case execution-time problem - overview of methods and survey of tools. (English)
ACM Trans Embed. Comput. Syst. 7, No. 3 (2008).
7
Enhancing the effectiveness of utilizing an instruction register file (English)
IPDPS, 1-5 (2008).
8
Guest editorial. (English)
ACM Trans Embed. Comput. Syst. 6, No. 1 (2007).
9
Evaluating heuristic optimization phase order search algorithms (English)
CGO, 157-169 (2007).
10
Fast, accurate design space exploration of embedded systems memory configurations (English)
SAC, 699-706 (2007).
11
Guaranteeing hits to improve the efficiency of a small instruction cache (English)
MICRO, 433-444 (2007).
12
Facilitating compiler optimizations through the dynamic mapping of alternate register structures (English)
CASES, 165-169 (2007).
13
Addressing instruction fetch bottlenecks by using an instruction register file (English)
LCTES, 165-174 (2007).
14
Generalizing parametric timing analysis (English)
LCTES, 152-154 (2007).
15
io-port 05452363 Kulkarni, Prasad;
Zhao, Wankang;
Hines, Stephen;
Whalley, David B.;
Yuan, Xin;
Van Engelen, Robert;
Gallivan, Kyle;
Hiser, Jason;
Davidson, Jack W.;
Cai, Baosheng;
Bailey, Mark W.;
Moon, Hwashin;
Cho, Kyunghwan;
Paek, Yunheung
VISTA: VPO interactive system for tuning applications. (English)
ACM Trans Embed. Comput. Syst. 5, No. 4, 819-863 (2006).
16
Improving WCET by applying worst-case path optimizations. (English)
Real-Time Syst. 34, No. 2, 129-152 (2006).
17
Exhaustive optimization phase order space exploration (English)
CGO, 306-318 (2006).
18
Adapting compilation techniques to enhance the packing of instructions into registers (English)
CASES, 43-53 (2006).
19
Reducing the cost of conditional transfers of control by using comparison specifications (English)
LCTES, 64-71 (2006).
20
Result 1 to 20 of 95 total
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