Result 1 to 20 of 236 total
RAFT: A router architecture with frequency tuning for on-chip networks. (English)
J. Parallel Distrib. Comput. 71, No. 5, 625-640 (2011).
1
Variation-aware task and communication mapping for mpsoc architecture. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 2, 295-307 (2011).
2
A case for heterogeneous on-chip interconnects for cmps (English)
ISCA, 389-400 (2011).
3
Architecting on-chip interconnects for stacked 3D STT-RAM caches in cmps (English)
ISCA, 69-80 (2011).
4
Total power optimization for combinational logic using genetic algorithms. (English)
J. Signal Process. Syst. Signal Image Video Technol. 58, No. 2, 145-160 (2010).
5
Total power optimization for combinational logic using genetic algorithms (English)
Signal Processing Systems 58, No. 2, 145-160 (2010).
6
Thermal gradient aware clock skew scheduling for fpgas (English)
FPL, 101-106 (2010).
7
A scalable bandwidth aware architecture for connected component labeling (English)
ISVLSI, 116-121 (2010).
8
A novel si-tunnel FET based SRAM design for ultra low-power 0.3V $V_{{\it DD}}$ applications (English)
ASP-DAC, 181-186 (2010).
9
A GPU based implementation of center-surround distribution distance for feature extraction and matching (English)
DATE, 172-177 (2010).
10
Investigating the impact of NBTI on different power saving cache strategies (English)
DATE, 592-597 (2010).
11
Compiler-assisted soft error detection under performance and energy constraints in embedded systems. (English)
ACM Trans Embed. Comput. Syst. 8, No. 4 (2009).
12
New-age: A negative bias temperature instability-estimation framework for microarchitectural components. (English)
Int. J. Parallel Program. 37, No. 4, 417-431 (2009).
13
Clone detection in sensor networks with {\it ad hoc} and grid topologies (English)
IJDSN 5, No. 3, 209-223 (2009).
14
A novel low area overhead body bias FPGA architecture for low power applications (English)
ISVLSI, 193-198 (2009).
15
A case for dynamic frequency tuning in on-chip networks (English)
MICRO, 292-303 (2009).
16
A framework for estimating NBTI degradation of microarchitectural components (English)
ASP-DAC, 455-460 (2009).
17
Exploiting clock skew scheduling for FPGA (English)
DATE, 1524-1529 (2009).
18
Design and evaluation of a hierarchical on-chip interconnect for next-generation cmps (English)
HPCA, 175-186 (2009).
19
Design space exploration for 3-D cache. (English)
IEEE Trans. VLSI Syst. 16, No. 4, 444-455 (2008).
20
Result 1 to 20 of 236 total
Start
Contact
Print
General Help
