Result 1 to 20 of 113 total
Topic 4: high-performance architecture and compilers. (English)
Kaklamanis, Christos (ed.) et al., Euro-Par 2012 parallel processing. 18th international conference, Euro-Par 2012, Rhodes Island, Greece, August 27‒31, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-32819-0/pbk). Lecture Notes in Computer Science 7484, 204-205 (2012).
1
Pruning hardware evaluation space via correlation-driven application similarity analysis (English)
Conf. Computing Frontiers, 4 (2011).
2
RELOCATE: Register file local access pattern redistribution mechanism for power and thermal management in out-of-order embedded processor. (English)
Patt, Yale N. (ed.) et al., High performance embedded architectures and compilers. 5th international conference, HiPEAC 2010, Pisa, Italy, January 25‒27, 2010. Proceedings. Berlin: Springer (ISBN 978-3-642-11514-1/pbk). Lecture Notes in Computer Science 5952, 216-231 (2010).
3
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks (English)
ISQED, 499-507 (2010).
4
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems (English)
ISLPED, 49-54 (2010).
5
Exploitation of nested thread-level speculative parallelism on multi-core systems (English)
Conf. Computing Frontiers, 99-100 (2010).
6
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units (English)
Conf. Computing Frontiers, 297-308 (2010).
7
On the efficacy of call graph-level thread-level speculation (English)
WOSP/SIPEW, 247-248 (2010).
8
RELOCATE: register file local access pattern redistribution mechanism for power and thermal management in out-of-order embedded processor (English)
HiPEAC, 216-231 (2010).
9
Brain derived vision algorithm on high performance architectures. (English)
Int. J. Parallel Program. 37, No. 4, 345-369 (2009).
10
On the exploitation of loop-level parallelism in embedded applications. (English)
ACM Trans Embed. Comput. Syst. 8, No. 2 (2009).
11
Performance characterization of Itanium$^{\circledR }$ 2-based Montecito processor. (English)
Kaeli, David (ed.) et al., Computer performance evaluation and benchmarking. SPEC benchmark workshop 2009, Austin, TX, USA, January 25, 2009. Proceedings. Berlin: Springer (ISBN 978-3-540-93798-2/pbk). Lecture Notes in Computer Science 5419, 36-56 (2009).
12
Performance characterization of itanium$\textregistered 2$-based montecito processor (English)
SPEC Benchmark Workshop, 36-56 (2009).
13
Power-aware load balancing of large scale MPI applications (English)
IPDPS, 1-8 (2009).
14
Efficient scheduling of nested parallel loops on multi-core systems (English)
ICPP, 74-83 (2009).
15
Synchronization optimizations for efficient execution on multi-cores (English)
ICS, 169-180 (2009).
16
Cache-aware partitioning of multi-dimensional iteration spaces (English)
SYSTOR, 15 (2009).
17
Efficient simulation of large-scale spiking neural networks using CUDA graphics processors (English)
IJCNN, 2145-2152 (2009).
18
Proceedings of the 6th conference on computing frontiers, 2009, Ischia, Italy, May 18-20, 2009 (English)
Conf. Computing Frontiers (2009).
19
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. (English)
Int. J. Embed. Syst. 3, No. 4, 285-293 (2008).
20
Result 1 to 20 of 113 total
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