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Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures (English)
Microelectronics Reliability 50, No. 9-11, 1636-1640 (2010).
WorldCat.org
1
3D stacked IC demonstrator using hybrid collective die-to-wafer bonding with copper through silicon vias (TSV) (English)
3DIC, 1-5 (2009).
WorldCat.org
4
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