Result 1 to 20 of 43 total
Compositional, dynamic cache management for embedded chip multiprocessors. (English)
J. Signal Process. Syst. Signal Image Video Technol. 57, No. 2, 155-172 (2009).
1
Compositional, dynamic cache management for embedded chip multiprocessors (English)
Signal Processing Systems 57, No. 2, 155-172 (2009).
2
Compositional memory systems for multimedia communicating tasks. (English)
Comput. Res. Repos. 2007, Article No. 0710.4658 (2007).
3
Static cache partitioning robustness analysis for embedded on-chip multi-processors (English)
T. HiPEAC 1, 279-297 (2007).
4
2D-to-3D TV image mapping on trimedias (English)
HPCNCS, 1-5 (2007).
5
Throughput optimization via cache partitioning for embedded multiprocessors (English)
ICSAMOS, 185-192 (2006).
6
Static cache partitioning robustness analysis for embedded on-chip multi-processors (English)
Conf. Computing Frontiers, 353-360 (2006).
7
Compositional, efficient caches for a chip multi-processor (English)
DATE, 345-350 (2006).
8
IEEE-compliant IDCT on FPGA-augmented TriMedia. (English)
J. VLSI Signal Process. Syst. Signal Image Video Technol. 39, No. 3, 195-212 (2005).
9
Hardwired MPEG-4 repetitive padding (English)
IEEE Transactions on Multimedia 7, No. 2, 261-268 (2005).
10
Compositional memory systems for multimedia communicating tasks (English)
DATE, 932-937 (2005).
11
Pel reconstruction on FPGA-augmented trimedia. (English)
IEEE Trans. VLSI Syst. 12, No. 6, 622-635 (2004).
12
Compositional memory systems for data intensive applications (English)
DATE, 728-729 (2004).
13
Application design trajectory towards reusable coprocessors MPEG case study (English)
ESTImedia, 33-38 (2004).
14
Color space conversion for MPEG decoding on FPGA-augmented trimedia processor (English)
ASAP, 250-259 (2003).
15
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks (English)
VLSI Design, 177-182 (2003).
16
Inter-cluster communication models for clustered VLIW processors (English)
HPCA, 354-364 (2003).
17
A Heterogeneous Multiprocessor Architecture for Flexible Media Processing. (English)
IEEE Design and Test of Computers 19, No.04, 39-50 (2002).
18
A 2D addressing mode for multimedia applications. (English)
Deprettere, Ed F. (ed.) et al., Embedded processor design challenges. Systems, architectures, modeling, and simulation - SAMOS. Berlin: Springer (ISBN 3-540-43322-8). Lect. Notes Comput. Sci. 2268, 291-306 (2002).
19
A reconfigurable functional unit for TriMedia/CPU64. A case study. (English)
Deprettere, Ed F. (ed.) et al., Embedded processor design challenges. Systems, architectures, modeling, and simulation - SAMOS. Berlin: Springer (ISBN 3-540-43322-8). Lect. Notes Comput. Sci. 2268, 224-241 (2002).
20
Result 1 to 20 of 43 total