Result 1 to 10 of 10 total
io-port 70226587 Van Der Plas, Geert;
Thijs, Steven;
Linten, Dimitri;
Katti, Guruprasad;
Limaye, Paresh;
Mercha, Abdelkarim;
Stucchi, Michele;
Oprins, Herman;
Vandevelde, Bart;
Minas, Nikolaos;
Cupac, Miro;
Dehan, Morin;
Nelis, Marc;
Agarwal, Rahul;
Dehaene, Wim;
Travaly, Youssef;
Beyne, Eric;
Marchal, Paul
Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - challenges and solutions (English)
CICC, 1-4 (2010).
1
TRAC: A platform for structure-function studies of NSS-proteins integrates information from bioinformatics and biomedical literature (English)
BIBE, 267-272 (2010).
3
ESD on-wafer characterization: is TLP still the right measurement tool? (English)
IEEE T. Instrumentation and Measurement 58, No. 10, 3418-3426 (2009).
4
io-port 50233259 Linten, Dimitri;
Thijs, Steven;
Borremans, Jonathan;
Dehan, Morin;
Trémouilles, D.;
Scholz, Mirko;
Natarajan, M. I.;
Wambacq, Piet;
Decoutere, Stefaan;
Groeseneken, Guido
A plug-and-play wideband RF circuit ESD protection methodology: T-diodes (English)
Microelectronics Reliability 49, No. 12, 1440-1446 (2009).
5
50-to-67GHz ESD-protected power amplifiers in digital 45nm LP CMOS (English)
ISSCC, 382-383 (2009).
6
Transient voltage overshoot in TLP testing - real or artifact? (English)
Microelectronics Reliability 47, No. 7, 1016-1024 (2007).
7
Implementation of plug-and-play ESD protection in 5.5GHz 90nm RF CMOS lnas - concepts, constraints and solutions (English)
Microelectronics Reliability 46, No. 5-6, 702-712 (2006).
8
ESD-RF co-design methodology for the state of the art RF-CMOS blocks (English)
Microelectronics Reliability 45, No. 2, 255-268 (2005).
9
High frequency characterization and modelling of the parasitic RC performance of two terminal ESD CMOS protection devices (English)
Microelectronics Reliability 43, No. 7, 1011-1020 (2003).
10
Result 1 to 10 of 10 total