Result 1 to 20 of 56 total
Lower $V_{DD}$ operation of FPGA-based digital circuits through delay modeling and time borrowing. (English)
J. Low Power Electron. 7, No. 2, 185-198 (2011).
1
Performance failure prediction using built-in delay sensors in fpgas (English)
FPL, 301-304 (2011).
2
Adaptive error-prediction flip-flop for performance failure prediction with aging sensors (English)
VTS, 203-208 (2011).
3
Low-sensitivity to process variations aging sensor for automotive safety-critical applications (English)
VTS, 238-243 (2010).
4
Programmable aging sensor for automotive safety-critical applications (English)
DATE, 618-621 (2010).
5
Automatic configuration of a medical imaging system to unknown delays in synchronous input data channels (English)
ISCAS, 1185-1188 (2010).
6
Predictive error detection by on-line aging monitoring (English)
IOLTS, 9-14 (2010).
7
Investigating the use of BICS to detect resistive-open defects in srams (English)
IOLTS, 200-201 (2010).
8
io-port 70683743 Leong, Carlos;
Machado, Pedro;
Bexiga, Vasco;
Teixeira, João Paulo;
Teixeira, Isabel C.;
Rego, Joel;
Neves, Pedro;
Piedade, Fernando;
Lousã, Pedro;
Rodrigues, Pedro;
Trindade, Andreia;
Bugalho, R.;
Pinheiro, J. F.;
Ferreira, Manuel;
Varela, João
Data acquisition electronics for PET mammography imaging (English)
BIODEVICES, 192-197 (2009).
9
Delay-fault tolerance to power supply voltage disturbances analysis in nanometer technologies (English)
IOLTS, 223-228 (2009).
11
Built-in aging monitoring for safety-critical applications (English)
IOLTS, 9-14 (2009).
12
Time management for low-power design of digital systems. (English)
J. Low Power Electron. 4, No. 3, 410-419 (2008).
13
Delay modeling for power noise and temperature-aware design and test of digital systems. (English)
J. Low Power Electron. 4, No. 3, 385-391 (2008).
14
Signal integrity enhancement in digital circuits (English)
IEEE Design & Test of Computers 25, No. 5, 452-461 (2008).
15
Process tolerant design using thermal and power-supply tolerance in pipeline based circuits (English)
DDECS, 34-37 (2008).
16
Exploiting parametric power supply and/or temperature variations to improve fault tolerance in digital circuits (English)
IOLTS, 227-232 (2008).
17
Enhancing the tolerance to power-supply instability in digital circuits (English)
ISVLSI, 207-212 (2007).
18
Improving the tolerance of pipeline based circuits to power supply or temperature variations (English)
DFT, 303-311 (2007).
19
Improving tolerance to power-supply and temperature variations in synchronous circuits (English)
DDECS, 295-300 (2007).
20
Result 1 to 20 of 56 total
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