io-port.net

io-port 05891348 Jhaveri, Tejas; Rovner, Vyacheslav; Liebmann, Lars; Pileggi, Larry T.; Strojwas, Andrzej J.; Hibbeler, Jason

Co-optimization of circuits, layout and lithography for predictive technology scaling beyond gratings. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29, No. 4, 509-527 (2010).

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io-port 70391338 Ns, Nagaraj; Rey, Juan C.; Kawa, Jamil; Aitken, Robert C.; Lütkemeyer, Christian; Pitchumani, Vijay; Strojwas, Andrzej J.; Trimberger, Steve

Who solves the variability problem? (English)

DAC, 218-219 (2010).

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io-port 70391837 Strojwas, Andrzej J.; Jhaveri, Tejas; Rovner, Vyacheslav; Pileggi, Lawrence T.

Creating an affordable 22nm node using design-lithography co-optimization (English)

DAC, 95-96 (2009).

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io-port 70691281 Casale-Rossi, Marco; Strojwas, Andrzej J.; Aitken, Robert C.; Domic, Antun; Guardiani, Carlo; Magarshack, Philippe; Pattullo, Douglas; Sawicki, Joseph

DFM/DFY: should you trust the surgeon or the family doctor? (English)

DATE, 439-442 (2007).

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io-port 05093501 Carballo, Juan-Antonio; Zorian, Yervant; Camposano, Raul; Strojwas, Andrzej J.; Kibarian, John K.; Wassung, Dennis; Alexanian, Alex; Wigley, Steve; Kelly, Neil

Guest Editors’ Introduction: DFM Drives Changes in Design Flow. (English)

IEEE Design and Test of Computers 22, No.03, 200-205 (2005).

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io-port 50355216 Carballo, Juan Antonio; Zorian, Yervant; Camposano, Raul; Strojwas, Andrzej J.; Kibarian, John; Wassung, Dennis; Alexanian, Alex; Wigley, Steve; Kelly, Neil

Guest editors’ introduction: DFM drives changes in design flow (English)

IEEE Design & Test of Computers 22, No. 3, 200-205 (2005).

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io-port 70110897 Zhan, Yaping; Strojwas, Andrzej J.; Sharma, Mahesh; Newmark, David

Statistical critical path analysis considering correlations (English)

PATMOS, 364-373 (2005).

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io-port 70232290 Strojwas, Andrzej J.

Tutorial on DFM for physical design (English)

ISPD, 103 (2005).

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io-port 70390026 Zhan, Yaping; Strojwas, Andrzej J.; Li, Xin; Pileggi, Lawrence T.; Newmark, David; Sharma, Mahesh

Correlation-aware statistical timing analysis with non-Gaussian delay distributions (English)

DAC, 77-82 (2005).

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io-port 70390737 Kheterpal, V.; Rovner, Vyacheslav; Hersan, T. G.; Motiani, D.; Takegawa, Y.; Strojwas, Andrzej J.; Pileggi, Lawrence T.

Design methodology for IC manufacturability based on regular logic-bricks (English)

DAC, 353-358 (2005).

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io-port 71010791 Zhan, Yaping; Strojwas, Andrzej J.; Sharma, Mahesh; Newmark, David

Statistical critical path analysis considering correlations (English)

ICCAD, 699-704 (2005).

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io-port 71011336 Li, Xin; Le, Jiayong; Pileggi, Lawrence T.; Strojwas, Andrzej J.

Projection-based performance modeling for inter/intra-die variations (English)

ICCAD, 721-727 (2005).

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io-port 70391347 Kheterpal, V.; Strojwas, Andrzej J.; Pileggi, Lawrence T.

Routing architecture exploration for regular fabrics (English)

DAC, 204-207 (2004).

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io-port 70391871 Strojwas, Andreas J.; Campbell, Michael; Gerousis, Vassilios; Hogan, Jim; Kibarian, John; Levitt, Marc; Ng, Walter; Pramanik, Dipu; Templeton, Mark

When IC yield missed the target, who is at fault? (English)

DAC, 80 (2004).

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io-port 05449264 Pandini, Davide; Pileggi, Lawrence T.; Strojwas, Andrzej J.

Global and local congestion optimization in technology mapping. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 22, No. 4, 498-505 (2003).

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io-port 70219283 Pandini, Davide; Pileggi, Lawrence T.; Strojwas, Andrzej J.

Bounding the efforts on congestion optimization for physical synthesis (English)

ACM Great Lakes Symposium on VLSI, 7-10 (2003).

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io-port 70389412 Pileggi, Lawrence T.; Schmit, Herman; Strojwas, Andrzej J.; Gopalakrishnan, Padmini; Kheterpal, V.; Koorapaty, Aneesh; Patel, Chetan; Rovner, Vyacheslav; Tong, K. Y.

Exploring regular fabrics to optimize the performance-cost trade-off (English)

DAC, 782-787 (2003).

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io-port 70232339 Pandini, Davide; Pileggi, Lawrence T.; Strojwas, Andrzej J.

Understanding and addressing the impact of wiring congestion during technology mapping (English)

ISPD, 131-136 (2002).

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io-port 70690106 Pandini, Davide; Pileggi, Lawrence T.; Strojwas, Andrzej J.

Congestion-aware logic synthesis (English)

DATE, 664-671 (2002).

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io-port 05449717 Sivaraman, Mukund; Strojwas, Andrzej J.

Path delay fault diagnosis and coverage-a metric and an estimationtechnique. (English)

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 20, No. 3, 440-457 (2001).

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