Result 1 to 20 of 83 total
Mixed-signal neuron-synapse implementation for large-scale neural network. (English)
Neurocomputing 69, No. 16-18, 1860-1867 (2006).
1
VHDL design of a scalable VLSI sorting device based on pipelined computation. (English)
J. Comput. Inf. Technol. 12, No. 1, 8-14 (2004).
2
Environment modelling for robot navigation using VLSI-efficient logarithmic approximation method. (English)
J. Intell. Robot. Syst. 35, No. 1, 23-40 (2002).
3
Parallel algorithms for solving linear equations in VLSI circuit simulation. (English)
Van Rienen, Ursula (ed.) et al., Scientific computing in electrical engineering. Proceedings of the 3rd international workshop, Warnemünde, Germany, August 20-23, 2000. Berlin: Springer. Lect. Notes Comput. Sci. Eng. 18, 301-308 (2001).
4
VLSI synthesis of DSP kernels. Algorithmic and architectural transformations. (English)
Boston: Kluwer Academic Publishers (ISBN 0-7923-7421-5). xxiii, 209~p. EUR~125.00; \$~115.00; \sterling~79.00 (2001).
5
Algorithms and theory of computation handbook. (English)
Boca Raton, FL: CRC Press. 980 p. DM 158,00; öS 1.154,00; sFr 143,00; \sterling 61,00; \$ 89,95 (1998).
6
Fixed-pipeline two-dimensional Hadamard transform algorithms. (English)
IEEE Trans. Signal Process. 45, No.6, 1669-1674 (1997).
7
A focal plane architecture for motion computation. (English)
Real-Time Imaging 2, No. 6, 351-360 (1996).
8
VLSI neural system architecture for finite ring recursive reduction. (English)
Int. J. Neural Syst. 7, No. 6, 697-708 (1996).
9
A new VLSI vector arithmetic coprocessor for workstations and the PC - technical data and realization. (English)
Z. Angew. Math. Mech. 76, Suppl. 1, 353-354 (1996).
10
Data broadcasting and reduction, prefix computation, and sorting on reduced hypercube parallel computers. (English)
Parallel Comput. 22, No.4, 595-606 (1996).
11
Handbook of neural computation. (English)
Bristol: Institute of Physics Publishing \& Oxford, New York: Oxford University Press. 1080 p. \sterling 275.00; \$ 395.00 (1996).
12
Analog VLSI neuromorphic image acquisition and pre-processing systems. (English)
Neural Netw. 8, No. 7-8, 1323-1347 (1995).
13
Area Time Trade-Offs in Micro-Grain VLSI Array Architectures. (English)
IEEE Transactions on Computers 43, No.10, 1121-1128 (1994).
14
A Cube-Connected Cycles Architecture with High Reliability and Improved Performance. (English)
IEEE Transactions on Computers 42, No.02, 246-253 (1993).
15
VLSI implementations of number theoretic techniques in signal processing. (English)
Integr., VLSI J. 16, No.3, 293-313 (1993).
16
Contribution to the numerical solution of the Laplace and heat equations. (Contribution à la résolution numérique des équations de Laplace et de la chaleur.) (French)
RAIRO, Modélisation Math. Anal. Numér. 27, No.5, 591-611 (1993).
17
An efficient algorithm and parallel implementations for binary and residue number systems. (English)
J. Symb. Comput. 15, No.4, 451-462 (1993).
18
Introduction to parallel processing. Transl. by Michele Re and Giovanni Cantatore. (English)
International Computing Science Series. Amsterdam etc.: Addison-Wesley Publishing Group. IX, 272 p. \$ 42.50 /sc (1993).
19
Delay-insensitive communication. (English)
Eindhoven: TU. VIII, 289 p. (1992).
20
Result 1 to 20 of 83 total
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