Result 1 to 19 of 19 total
Reconfigurable instruction decoding for a wide-control-word processor (English)
IPDPS Workshops, 322-325 (2011).
1
Power-aware resource scheduling in base stations (English)
MASCOTS, 462-465 (2011).
2
A high-speed, energy-efficient two-cycle multiply-accumulate (MAC) architecture and its application to a double-throughput MAC unit (English)
IEEE Trans. on Circuits and Systems 57-I, No. 12, 3073-3081 (2010).
3
Design space exploration for an embedded processor with flexible datapath interconnect (English)
ASAP, 55-62 (2010).
4
FlexCore: utilizing exposed datapath control for efficient computing. (English)
J. Signal Process. Syst. Signal Image Video Technol. 57, No. 1, 5-19 (2009).
5
A flexible code compression scheme using partitioned look-up tables. (English)
Seznec, André (ed.) et al., High performance embedded architectures and compilers. Fourth international conference, HiPEAC 2009, Paphos, Cyprus, January 25‒28, 2009. Proceedings. Berlin: Springer (ISBN 978-3-540-92989-5/pbk). Lecture Notes in Computer Science 5409, 95-109 (2009).
6
Flexcore: utilizing exposed datapath control for efficient computing (English)
Signal Processing Systems 57, No. 1, 5-19 (2009).
7
Scheduling for an embedded architecture with a flexible datapath (English)
ISVLSI, 151-156 (2009).
8
Double throughput multiply-accumulate unit for flexcore processor enhancements (English)
IPDPS, 1-7 (2009).
9
Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree (English)
ICECS, 77-80 (2009).
10
High-speed, energy-efficient 2-cycle multiply-accumulate architecture (English)
SoCC, 119-122 (2009).
11
A flexible code compression scheme using partitioned look-up tables (English)
HiPEAC, 95-109 (2009).
12
Early detection and bypassing of trivial operations to improve energy efficiency of processors (English)
Microprocessors and Microsystems - Embedded Hardware Design 32, No. 4, 183-196 (2008).
13
A look-ahead task management unit for embedded multi-core architectures (English)
DSD, 149-157 (2008).
14
Flexcore: utilizing exposed datapath control for efficient computing (English)
ICSAMOS, 18-25 (2007).
15
A flexible datapath interconnect for embedded applications (English)
ISVLSI, 15-20 (2007).
16
Multiplier reduction tree with logarithmic logic depth and regular connectivity (English)
ISCAS (2006).
17
A low-leakage twin-precision multiplier using reconfigurable power gating (English)
ISCAS (2), 1654-1657 (2005).
18
An efficient twin-precision multiplier (English)
ICCD, 30-33 (2004).
19
Result 1 to 19 of 19 total
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