Result 1 to 12 of 12 total
Runtime-datapath-remapping for fault-tolerant coarse-grained reconfigurable architectures (English)
ReCoSoC, 1-2 (2011).
1
Low energy voltage dithering in dual $V_{DD}$ circuits. (English)
Monteiro, José (ed.) et al., Integrated circuit and system design. Power and timing modeling, optimization and simulation. 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009. Revised selected papers. Berlin: Springer (ISBN 978-3-642-11801-2/pbk). Lecture Notes in Computer Science 5953, 237-246 (2010).
2
Evaluation and design methods for processor-like reconfigurable architectures (English)
Dynamically Reconfigurable Systems, 95-116 (2010).
3
Low energy voltage dithering in dual $V_{{\it DD}}$ circuits (English)
PATMOS, 237-246 (2009).
4
Prevention of hot spot development on coarse-grained dynamically reconfigurable architectures (English)
ReConFig, 12-17 (2009).
5
Optimizing partial reconfiguration of multi-context architectures (English)
ReConFig, 67-72 (2008).
7
CRC - concepts and evaluation of processor-like reconfigurable architectures (CRC - konzepte und bewertung prozessorartig rekonfigurierbarer architekturen). (English)
it Inf. Technol. 49, No. 3, 157- (2007).
8
The cerebellum mediates conflict resolution (English)
J. Cognitive Neuroscience 19, No. 12, 1974-1982 (2007).
9
Evaluation of ray casting on processor-like reconfigurable architectures (English)
FPL, 185-190 (2005).
10
A design environment for processor-like reconfigurable hardware (English)
PARELEC, 171-176 (2004).
11
Object-oriented modeling and synthesis of systemc specifications (English)
ASP-DAC, 238-243 (2004).
12
Result 1 to 12 of 12 total
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