Result 1 to 20 of 37 total
Low-complexity inverse square root approximation for baseband matrix operations. (English)
ISRN Signal Process. 2011, Article ID 615934, 8 p. (2011).
1
Design methodology for offloading software executions to FPGA (English)
Signal Processing Systems 65, No. 2, 245-259 (2011).
2
Fixed- versus floating-point implementation of MIMO-OFDM detector (English)
ICASSP, 3276-3279 (2011).
3
Conjugacy of finite biprefix codes. (English)
Theor. Comput. Sci. 410, No. 24-25, 2345-2351 (2009).
4
3G long term evolution baseband processing with application-specific processors (English)
Int. J. Digital Multimedia Broadcasting 2009 (2009).
5
Reconfigurable video decoder with transform acceleration (English)
SiPS, 081-086 (2009).
6
A programmable Max-log-MAP turbo decoder implementation. (English)
VLSI Des. 2008, Article ID 319095, 17 p. (2008).
7
An experimental evaluation of a HIP based network mobility scheme. (English)
Harju, Jarmo (ed.) et al., Wired/wireless internet communications. 6th international conference, WWIC 2008 Tampere, Finland, May 28‒30, 2008. Proceedings. Berlin: Springer (ISBN 978-3-540-68805-1/pbk). Lecture Notes in Computer Science 5031, 139-151 (2008).
8
A programmable Max-\log -MAP turbo decoder implementation (English)
VLSI Design 2008 (2008).
9
Fine-grained application-specific instruction set processor design for the K-best list sphere detector algorithm (English)
ICSAMOS, 108-115 (2008).
10
Complex-valued QR decomposition implementation for MIMO receivers (English)
ICASSP, 1433-1436 (2008).
11
Low-complexity polynomials modulo integer with linearly incremented variable (English)
SiPS, 251-256 (2008).
12
An experimental evaluation of a HIP based network mobility scheme (English)
WWIC, 139-151 (2008).
13
Performance analysis of HIP-based mobility and triggering (English)
WOWMOM, 1-9 (2008).
14
Stride permutation networks for array processors. (English)
J. VLSI Signal Process. Syst. Signal Image Video Technol. 49, No. 1, 51-71 (2007).
15
Application-specific instruction set processor implementation of list sphere detector (English)
EURASIP J. Emb. Sys. 2007 (2007).
16
Memory-based list updating for list sphere decoders (English)
SiPS, 633-638 (2007).
17
Synthesis of DSP architectures using libraries of coarse-grain configurations (English)
SiPS, 475-480 (2007).
18
On the simplest centralizer of a language. (English)
Rev. Inform. Teor. Apl. 40, No. 2, 295-301 (2006).
19
On the simplest centralizer of a language. (English)
Theor. Inform. Appl. 40, No. 2, 295-301 (2006).
20
Result 1 to 20 of 37 total
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