Predictable task migration for locked caches in multi-core systems (English)
LCTES, 131-140 (2011).
1
Tightening the bounds on feasible preemptions. (English)
ACM Trans Embed. Comput. Syst. 10, No. 2, 27 (2010).
2
Bounding worst-case response times of tasks under PIP (English)
IEEE Real-Time and Embedded Technology and Applications Symposium, 183-192 (2009).
3
Push-assisted migration of real-time tasks in multi-core processors (English)
LCTES, 80-89 (2009).
4
Bounding worst-case response time for tasks with non-preemptive regions (English)
IEEE Real-Time and Embedded Technology and Applications Symposium, 58-67 (2008).
5
Tightening the bounds on feasible preemption points (English)
RTSS, 212-224 (2006).
6
Bounding preemption delay within data cache reference patterns for real-time tasks (English)
IEEE Real Time Technology and Applications Symposium, 71-80 (2006).
7
Bounding worst-case data cache behavior by analytically deriving cache reference patterns (English)
IEEE Real-Time and Embedded Technology and Applications Symposium, 148-157 (2005).
8
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