Result 1 to 20 of 288 total
VLSI architecture for bit parallel systolic multipliers for special class of GF$(2^{m })$ using dual bases. (English)
Rahaman, Hafizur (ed.) et al., Progress in VLSI design and test. 16th international symposium, VDAT 2012, Shibpur, India, July 1‒4, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-31493-3/pbk). Lecture Notes in Computer Science 7373, 258-269 (2012).
1
Complexity of distance paired-domination problem in graphs. (English)
Theor. Comput. Sci. 459, 89-99 (2012).
2
Algorithmic aspects of $k$-tuple total domination in graphs. (English)
Inf. Process. Lett. 112, No. 21, 816-822 (2012).
3
Complexity of certain functional variants of total domination in chordal bipartite graphs. (English)
Discrete Math. Algorithms Appl. 4, No. 3, 1250045,19p. (2012).
4
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM. (English)
Integr., VLSI J. 45, No. 1, 33-45 (2012).
5
Pseudo-parallel datapath structure for power optimal implementation of 128-pt FFT/IFFT for WPAN. (English)
Circuits Syst. Signal Process. 30, No. 4, 871-882 (2011).
6
Matrix codes for reliable and cost efficient memory chips. (English)
IEEE Trans. VLSI Syst. 19, No. 3, 420-428 (2011).
7
A Robin-type non-overlapping domain decomposition procedure for second order elliptic problems. (English)
Adv. Comput. Math. 34, No. 4, 339-368 (2011).
8
Reliability analysis of H-tree random access memories implemented with built in current sensors and parity codes for multiple bit upset correction (English)
IEEE Transactions on Reliability 60, No. 3, 528-537 (2011).
9
Fault tolerant single error correction encoders (English)
J. Electronic Testing 27, No. 2, 215-218 (2011).
10
BCH code based multiple bit error correction in finite field multiplier circuits (English)
ISQED, 615-620 (2011).
11
A dynamically error correctable bit parallel montgomery multiplier over binary extension fields (English)
ECCTD, 600-603 (2011).
12
Test generation in systolic architecture for multiplication over GF($2 ^{m}$). (English)
IEEE Trans. VLSI Syst. 18, No. 9, 1366-1371 (2010).
13
DOE-ILP based simultaneous power and read stability optimization in nano-CMOS SRAM. (English)
J. Low Power Electron. 6, No. 3, 390-400 (2010).
14
Clustered de Bruijn based multi layered architectures for sensor networks. (English)
Özcan, Abdulkadir (ed.) et al., Recent trends in wireless and mobile networks. Second international conference, WiMo 2010, Ankara, Turkey, June 26‒28, 2010. Proceedings. Berlin: Springer (ISBN 978-3-642-14170-6/pbk; 978-3-642-14171-3/ebook). Communications in Computer and Information Science 84, 123-136 (2010).
15
Introduction to design techniques for energy harvesting (English)
JETC 6, No. 2 (2010).
16
ULS: A dual-${\it v_{th}}$/high-kappa nano-CMOS universal level shifter for system-level power management (English)
JETC 6, No. 2 (2010).
17
Secure testable S-box architecture for cryptographic hardware implementation (English)
Comput. J. 53, No. 5, 581-591 (2010).
18
Simplified bit parallel systolic multipliers for special class of Galois field $(2^{m})$ with testability (English)
IET Computers & Digital Techniques 4, No. 5, 428-437 (2010).
19
A Galois field-based logic synthesis with testability (English)
IET Computers & Digital Techniques 4, No. 4, 263-273 (2010).
20
Result 1 to 20 of 288 total
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