Result 1 to 20 of 42 total
Parsimonious circuits for error-tolerant applications through probabilistic logic minimization. (English)
Ayala, José L. (ed.) et al., Integrated circuit and system design. Power and timing modeling, optimization, and simulation. 21st international workshop, PATMOS 2011, Madrid, Spain, September 26‒29, 2011. Proceedings. Berlin: Springer (ISBN 978-3-642-24153-6/pbk). Lecture Notes in Computer Science 6951, 204-213 (2011).
1
Optimal logic architecture and supply voltage selection method to reduce the impact of the threshold voltage variation on the timing. (English)
J. Low Power Electron. 7, No. 2, 285-293 (2011).
2
Logic architecture and VDD selection for reducing the impact of intra-die random $V_{T}$ variations on timing. (English)
van Leuken, René (ed.) et al., Integrated circuit and system design. Power and timing modeling, optimization, and simulation. 20th international workshop, PATMOS 2010, Grenoble, France, September 7‒10, 2010. Revised selected papers. Berlin: Springer (ISBN 978-3-642-17751-4/pbk). Lecture Notes in Computer Science 6448, 170-179 (2011).
3
Guest editorial special issue on ISCAS 2010 (English)
IEEE Trans. on Circuits and Systems 58-I, No. 7, 1457 (2011).
4
Bringing robustness and power efficiency to autonomous energy-harvesting microsystems (English)
IEEE Design & Test of Computers 28, No. 5, 84-94 (2011).
5
Parsimonious circuits for error-tolerant applications through probabilistic logic minimization (English)
PATMOS, 204-213 (2011).
6
Energy parsimonious circuit design through probabilistic pruning (English)
DATE, 764-769 (2011).
7
A refinement methodology for clock gating optimization at layout level in digital circuits. (English)
J. Low Power Electron. 6, No. 1, 44-55 (2010).
8
VLSI-SoC: Design methodologies for SoC and SiP. 16th IFIP WG 10.5/IEEE international conference on very large scale integration, VLSI-SoC 2008, Rhodes Island, Greece, October 13‒15, 2008. Revised selected papers. (English)
IFIP Advances in Information and Communication Technology 313. Berlin: Springer (ISBN 978-3-642-12266-8/hbk; 978-3-642-12267-5/ebook). viii, 287~p. EUR~83.46 (2010).
9
io-port 50130947 Belleville, Marc;
Fanet, H.;
Fiorini, Paolo;
Nicole, P.;
Pelgrom, M. J. M.;
Piguet, Christian;
Hahn, R.;
Van Hoof, Chris;
Vullers, Ruud J. M.;
Tartagni, Marco;
Cantatore, Eugenio
Energy autonomous sensor systems: towards a ubiquitous sensor technology (English)
Microelectronics Journal 41, No. 11, 740-745 (2010).
10
Logic architecture and VDD selection for reducing the impact of intra-die random $V_{T}$ variations on timing (English)
PATMOS, 170-179 (2010).
11
AVGS-mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics (English)
DATE, 339-344 (2010).
12
Reverse Vgs static CMOS (RVGS-SCMOS); A new technique for dynamically compensating the process variations in sub-threshold designs. (English)
Svensson, Lars (ed.) et al., Integrated circuit and system design. Power and timing modeling, optimization and simulation. 18th international workshop, PATMOS 2008, Lisbon, Portugal, September 10‒12, 2008. Revised selected papers. Berlin: Springer (ISBN 978-3-540-95947-2/pbk). Lecture Notes in Computer Science 5349, 11-20 (2009).
13
Low-power heterogeneous systems-on-chips. (English)
J. Low Power Electron. 4, No. 2, 111-126 (2008).
14
Reverse vgs static CMOS (RVGS-SCMOS); A new technique for dynamically compensating the process variations in sub-threshold designs (English)
PATMOS, 11-20 (2008).
15
Chronique : consommation statique. Modèles, évolutions et perspectives (English)
Technique et Science Informatiques 26, No. 5, 623-638 (2007).
16
Static and dynamic power reduction by architecture selection (English)
PATMOS, 659-668 (2006).
17
Architectural and technology influence on the optimal total power consumption (English)
DATE, 989-994 (2006).
18
An architecture design methodology for minimal total power consumption at fixed vdd and vth. (English)
J. Low Power Electron. 1, No. 1, 3-10 (2005).
19
Low-power CMOS circuits - technology, logic design and CAD tools (English)
Low-power CMOS circuits - technology, logic design and CAD tools (2005).
20
Result 1 to 20 of 42 total
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