Result 1 to 20 of 55 total
Scalable communications for a million-core neural processing architecture. (English)
J. Parallel Distrib. Comput. 72, No. 11, 1507-1520 (2012).
1
Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware. (English)
Neural Netw. 24, No. 9, 961-978 (2011).
2
io-port 05970226 Khan, M.M.;
Rast, A.D.;
Navaridas, J.;
Jin, X.;
Plana, L.A.;
Luján, M.;
Temple, S.;
Patterson, C.;
Richards, D.;
Woods, J.V.;
Miguel-Alonso, J.;
Furber, S.B.
Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric. (English)
Parallel Comput. 37, No. 8, 392-409 (2011).
3
Thwarting software attacks on data-intensive platforms with configurable hardware-assisted application rule enforcement (English)
FPL, 207-212 (2011).
4
Improved abstractions and turnaround time for FPGA design validation and debug (English)
FPL, 518-523 (2011).
5
Metawire: using FPGA configuration circuitry to emulate a network-on-chip (English)
IET Computers & Digital Techniques 4, No. 3, 159-169 (2010).
6
Implementation of a low cost, lightweight X-band antenna with integrated sige RF electronics (English)
IGARSS, 681-684 (2010).
7
Using partial reconfiguration and high-level models to accelerate FPGA design validation (English)
FPT, 341-344 (2010).
8
Accelerating FPGA development through the automatic parallel application of standard implementation tools (English)
FPT, 53-60 (2010).
9
PATIS: using partial configuration to improve static FPGA design productivity (English)
IPDPS Workshops, 1-8 (2010).
10
Scalable event-driven native parallel processing: the spinnaker neuromimetic system (English)
Conf. Computing Frontiers, 21-30 (2010).
11
Algorithm and software for simulation of spiking neural networks on the multi-chip spinnaker system (English)
IJCNN, 1-8 (2010).
12
Slotless module-based reconfiguration of embedded fpgas. (English)
ACM Trans Embed. Comput. Syst. 9, No. 1 (2009).
13
Searching for transient pulses with the ETA radio telescope (English)
TRETS 1, No. 4 (2009).
14
Data streaming and simd support for the microblaze architecture (English)
FPGA, 277 (2009).
15
Exploiting process locality of reference in RTL simulation acceleration. (English)
EURASIP J. Embed. Syst. 2008, Article ID 369040, 10 p. (2008).
16
Exploiting process locality of reference in RTL simulation acceleration (English)
EURASIP J. Emb. Sys. 2008 (2008).
17
An efficient run-time router for connecting modules in FPGAS (English)
FPL, 125-130 (2008).
18
Metawire: using FPGA configuration circuitry to emulate a network-on-chip (English)
FPL, 257-262 (2008).
19
Human-centered space design for the homeless: clean dignity (English)
CHI Extended Abstracts, 3831-3836 (2008).
20
Result 1 to 20 of 55 total
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