Result 1 to 20 of 25 total
Mining ontological knowledge using nyaya framework. (English)
Int. J. Netw. Virtual Organ. 8, No. 1-2, 123-141 (2011).
1
A multilevel UNL concept based searching and ranking (English)
WEBIST, 282-289 (2011).
2
Practical and scalable evolution of digital circuits. (English)
Appl. Soft. Comput. 9, No. 2, 618-624 (2009).
3
Architecture for an active network infrastructure grid ‒ the iSEGrid. (English)
Hutchison, David (ed.) et al., Active and programmable networks. IFIP TC6 7th international working conference, IWAN 2005, Sophia Antipolis, France, November 21‒23, 2005. Revised papers. Berlin: Springer (ISBN 978-3-642-00971-6/pbk). Lecture Notes in Computer Science 4388, 38-52 (2009).
4
An inevitable collision state-checker for a car-like vehicle (English)
ICRA, 3068-3073 (2007).
5
Mobile ad hoc grid using trace based mobility model (English)
GPC, 274-285 (2007).
6
Trace based mobility model for ad hoc networks (English)
WiMob, 81 (2007).
7
Evaluating the network processor architecture for application-awareness (English)
COMSWARE (2007).
8
An ASM model for an autonomous network-infrastructure grid (English)
ICNS, 29 (2007).
9
Genetic learning based fault tolerant models for digital systems. (English)
Appl. Soft. Comput. 5, No. 4, 357-371 (2005).
10
A novel self-organizing neural fuzzy network for automatic generation of fuzzy inference systems. (English)
Wang, Jun (ed.) et al., Advances in neural networks ‒ ISNN 2005. Second international symposium on neural networks, Chongqing, China, May 30 ‒ June 1, 2005. Proceedings, Part I. Berlin: Springer (ISBN 3-540-25912-0/pbk). Lecture Notes in Computer Science 3496, 434-439 (2005).
11
A novel self-organizing neural fuzzy network for automatic generation of fuzzy inference systems (English)
ISNN (1), 434-439 (2005).
12
Architecture for an active network infrastructure grid - the {\it isegrid} (English)
IWAN, 38-52 (2005).
13
Evolution of asynchronous sequential circuits (English)
Evolvable Hardware, 93-96 (2005).
14
An active framework for a WLAN access point using intel’s IXP1200 network processor (English)
HiPC, 71-80 (2004).
15
Enhancing the development based evolution of digital circuits (English)
Evolvable Hardware, 91- (2004).
16
Jbits based fault tolerant framework for evolvable hardware (English)
Engineering of Reconfigurable Systems and Algorithms, 111-117 (2003).
17
Live-cache: exploiting data redundancy to reduce leakage energy in a cache subsystem (English)
Asia-Pacific Computer Systems Architecture Conference, 337-351 (2003).
18
Exploring FPGA structures for evolving fault tolerant hardware (English)
Evolvable Hardware, 184-191 (2003).
19
Dead-block elimination in cache: A mechanism to reduce I-cache power consumption in high performance microprocessors. (English)
Sahni, Sartaj (ed.) et al., High performance computing - HiPC 2002. 9th international conference, Bangalore, India, December 18-21, 2002. Proceedings. Berlin: Springer. Lect. Notes Comput. Sci. 2552, 79-88 (2002).
20
Result 1 to 20 of 25 total
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