io-port.net

io-port 70543001 Alampally, S.; Venkatesh, R. T.; Shanmugasundaram, P.; Parekhji, Rubin A.; Agrawal, V. D.

An efficient test data reduction technique through dynamic pattern mixing across multiple fault models (English)

VTS, 285-290 (2011).

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io-port 70887947 Prasanth, V.; Singh, Virendra; Parekhji, Rubin A.

Reduced overhead soft error mitigation using error control coding techniques (English)

IOLTS, 163-168 (2011).

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io-port 50353259 Reddy, M. Kiran Kumar; Amrutur, Bharadwaj S.; Parekhji, Rubin A.

False error vulnerability study of on-line soft error detection mechanisms (English)

J. Electronic Testing 26, No. 3, 323-335 (2010).

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io-port 70542381 Sabne, Amit; Tiwari, Rajesh; Shrivastava, Abhijeet; Ravi, Srivaths; Parekhji, Rubin A.

A generic low power scan chain wrapper for designs using scan compression (English)

VTS, 135-140 (2010).

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io-port 70542639 Parekhji, Rubin A.

Innovative practices session 1C: innovative practices in RF test (English)

VTS, 39 (2010).

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io-port 70542791 Mittal, R.; Sontakke, Sontakke; Parekhji, Rubin A.

Test time reduction using parallel RF test techniques (English)

VTS, 40 (2010).

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io-port 70887929 Prasanth, V.; Singh, Virendra; Parekhji, Rubin A.

Robust detection of soft errors using delayed capture methodology (English)

IOLTS, 277-282 (2010).

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io-port 70180463 Fang, Hongxia; Chakrabarty, Krishnendu; Parekhji, Rubin A.

Bit-operation-based seed augmentation for LFSR reseeding with high defect coverage (English)

Asian Test Symposium, 331-336 (2009).

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io-port 70888363 Dutta, Amit; Shah, Malav; Swathi, G.; Parekhji, Rubin A.

Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test (English)

IOLTS, 237-242 (2009).

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io-port 05765447 Ravi, Srivaths; Parekhji, Rubin A.; Saxena, Jayashree

Low power test for nanometer system-on-chips (SoCs). (English)

J. Low Power Electron. 4, No. 1, 81-100 (2008).

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io-port 70542801 Tiwari, Rajesh; Shrivastava, Abhijeet; Warhadpande, Mahit; Ravi, Srivaths; Parekhji, Rubin A.

A regression based technique for ATE-aware test data volume estimation of system-on-chips (English)

VTS, 53-58 (2008).

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io-port 70888102 Reddy, M. Kiran Kumar; Amrutur, Bharadwaj S.; Parekhji, Rubin A.

False error study of on-line soft error detection mechanisms (English)

IOLTS, 53-58 (2008).

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io-port 70973719 Surendran, Sudhakar; Parekhji, Rubin A.; Govindarajan, R.

A systematic approach to synthesis of verification test-suites for modular soc designs (English)

SoCC, 91-96 (2008).

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io-port 70639140 Roy, Subir K.; Parekhji, Rubin A.

Modeling techniques for formal verification of BIST controllers and their integration into SOC designs (English)

VLSI Design, 364-372 (2007).

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io-port 70640642 Jain, Sandeep; Abraham, Jais; Vooka, Srinivas Kumar; Kale, Sumant; Dutta, Amit; Parekhji, Rubin A.

Enhancements in deterministic BIST implementations for improving test of complex socs (English)

VLSI Design, 339-344 (2007).

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io-port 70640761 Yada, Satish; Amrutur, Bharadwaj S.; Parekhji, Rubin A.

Modified stability checking for on-line error detection (English)

VLSI Design, 787-792 (2007).

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io-port 71011329 Ravi, Srivaths; Devanathan, V. R.; Parekhji, Rubin A.

Methodology for low power test pattern generation using activity threshold control logic (English)

ICCAD, 526-529 (2007).

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io-port 70543035 Parekhji, Rubin A.

Session abstract (English)

VTS, 86-87 (2006).

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io-port 70180366 Parekhji, Rubin A.

DFT for low cost SOC test (English)

Asian Test Symposium, 451 (2005).

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io-port 70180852 Goel, Sameer; Parekhji, Rubin A.

Choosing the right mix of at-speed structural test patterns: comparisons in pattern volume reduction and fault detection efficiency (English)

Asian Test Symposium, 330-336 (2005).

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