Result 1 to 20 of 72 total
A quick method for energy-optimized gate sizing of digital circuits. (English)
Ayala, José L. (ed.) et al., Integrated circuit and system design. Power and timing modeling, optimization, and simulation. 21st international workshop, PATMOS 2011, Madrid, Spain, September 26‒29, 2011. Proceedings. Berlin: Springer (ISBN 978-3-642-24153-6/pbk). Lecture Notes in Computer Science 6951, 1-10 (2011).
1
A quick method for energy optimized gate sizing of digital circuits (English)
PATMOS, 1-10 (2011).
2
Multiplier structures for low power applications in deep-CMOS (English)
ISCAS, 1061-1064 (2011).
3
Low-power soft error hardened latch. (English)
J. Low Power Electron. 6, No. 1, 218-226 (2010).
4
A new methodology for power-aware transistor sizing: Free Power Recovery (FPR). (English)
Monteiro, José (ed.) et al., Integrated circuit and system design. Power and timing modeling, optimization and simulation. 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009. Revised selected papers. Berlin: Springer (ISBN 978-3-642-11801-2/pbk). Lecture Notes in Computer Science 5953, 307-316 (2010).
5
Low-power soft error hardened latch. (English)
Monteiro, José (ed.) et al., Integrated circuit and system design. Power and timing modeling, optimization and simulation. 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009. Revised selected papers. Berlin: Springer (ISBN 978-3-642-11801-2/pbk). Lecture Notes in Computer Science 5953, 256-265 (2010).
6
Energy efficient implementation of parallel CMOS multipliers with improved compressors (English)
ISLPED, 147-152 (2010).
7
Computing at the ultimate low-energy limits (English)
SBCCI, 1 (2010).
8
Design of a link-controller architecture for multiple serial link protocols (English)
SoCC, 266-271 (2010).
9
Proceedings of the 2010 international symposium on low power electronics and design, 2010, Austin, Texas, USA, August 18-20, 2010 (English)
ISLPED (2010).
10
Energy efficiency of power-gating in low-power clocked storage elements. (English)
Svensson, Lars (ed.) et al., Integrated circuit and system design. Power and timing modeling, optimization and simulation. 18th international workshop, PATMOS 2008, Lisbon, Portugal, September 10‒12, 2008. Revised selected papers. Berlin: Springer (ISBN 978-3-540-95947-2/pbk). Lecture Notes in Computer Science 5349, 268-276 (2009).
11
A new methodology for power-aware transistor sizing: free power recovery (FPR) (English)
PATMOS, 307-316 (2009).
12
Low-power soft error hardened latch (English)
PATMOS, 256-265 (2009).
13
Jitter analysis of nonautonomous MOS current-mode logic circuits (English)
IEEE Trans. on Circuits and Systems 55-I, No. 10, 3038-3049 (2008).
14
Reduced instruction set computing (English)
Wiley Encyclopedia of Computer Science and Engineering (2008).
15
Energy efficiency of power-gating in low-power clocked storage elements (English)
PATMOS, 268-276 (2008).
16
Proceedings of the 2008 international symposium on low power electronics and design, 2008, Bangalore, India, August 11-13, 2008 (English)
ISLPED (2008).
17
Logic style comparison for ultra low power operation in 65nm technology (English)
PATMOS, 181-190 (2007).
18
Energy optimization of pipelined digital systems using circuit sizing and supply scaling. (English)
IEEE Trans. VLSI Syst. 14, No. 2, 122-134 (2006).
19
Circuit sizing and supply-voltage selection for low-power digital circuit design (English)
PATMOS, 148-156 (2006).
20
Result 1 to 20 of 72 total
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