Result 1 to 20 of 28 total
Parallelization strategies for ant colony optimisation on gpus. (English)
Comput. Res. Repos. 2011, Article No. 1101.2678 (2011).
1
Performance evaluation of secure key deployment and exchange protocol for manets (English)
IJSSE 2, No. 1, 1-21 (2011).
2
High-efficiency server design (English)
SC, 27 (2011).
3
Parallelization strategies for ant colony optimisation on gpus (English)
IPDPS Workshops, 339-346 (2011).
4
The quest for optimum server location selection in mobile ad hoc networks utilising threshold cryptography (English)
ITNG, 891-896 (2010).
5
A stochastic bitwidth estimation technique for compact and low-power custom processors. (English)
ACM Trans Embed. Comput. Syst. 7, No. 3 (2008).
6
Capacity planning for service-oriented architectures (English)
CASCON, 11 (2008).
7
Estimating data bus size for custom processors in embedded systems. (English)
Des. Autom. Embed. Syst. 10, No. 1, 5-26 (2005).
8
High performance scientific computing using fpgas with IEEE floating point and logarithmic arithmetic for lattice QCD (English)
FPL, 1-6 (2006).
9
GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems (English)
FPGA, 236 (2006).
10
The case for virtual register machines. (English)
Sci. Comput. Program. 57, No. 3, 319-338 (2005).
11
Estimating data bus size for custom processors in embedded systems (English)
Design Autom. for Emb. Sys. 10, No. 1, 5-26 (2005).
12
FPGA implementation of a lattice quantum chromodynamics algorithm using logarithmic arithmetic (English)
IPDPS (2005).
13
Stochastic bit-width approximation using extreme value theory for customizable processors. (English)
Duesterwald, Evelyn (ed.), Compiler construction. 13th international conference, CC 2004, held as part of the joint European conferences on theory and practice of software, ETAPS 2004, Barcelona, Spain, March 29 ‒ April 2, 2004. Proceedings. Berlin: Springer (ISBN 3-540-21297-3/pbk). Lecture Notes in Computer Science 2985, 250-264 (2004).
14
Automatic customization of embedded applications for enhanced performance and reduced power using optimizing compiler techniques. (English)
Danelutto, Marco (ed.) et al., Euro-Par 2004, parallel processing. 10th international Euro-Par conference, Pisa, Italy, August 31 ‒ September 3, 2004. Proceedings. Berlin: Springer (ISBN 3-540-22924-8/pbk). Lecture Notes in Computer Science 3149, 318-327 (2004).
15
Automatic customization of embedded applications for enhanced performance and reduced power using optimizing compiler techniques (English)
Euro-Par, 318-327 (2004).
16
Fine-tuning loop-level parallelism for increasing performance of DSP applications on fpgas (English)
FCCM, 273-274 (2004).
17
A systems architecture for sensor networks based on hardware/software co-design (English)
WAC, 115-126 (2004).
18
Stochastic bit-width approximation using extreme value theory for customizable processors (English)
CC, 250-264 (2004).
19
Towards superinstructions for Java interpreters (English)
SCOPES, 329-343 (2003).
20
Result 1 to 20 of 28 total
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