Result 1 to 20 of 23 total
FIFA: A fault-injection-fault-analysis-based tool for reliability assessment at RTL level (English)
Microelectronics Reliability 51, No. 9-11, 1459-1463 (2011).
1
Reliability aware design of low power continuous-time sigma-delta modulator (English)
Microelectronics Reliability 51, No. 9-11, 1449-1453 (2011).
2
A synthesis methodology for AMS/RF circuit reliability: application to a DCO design (English)
Microelectronics Reliability 51, No. 4, 765-772 (2011).
3
A new synthesis methodology for reliable RF front-end design (English)
ISCAS, 2926-2929 (2011).
4
Using error tolerance of target application for efficient reliability improvement of digital circuits (English)
Microelectronics Reliability 50, No. 9-11, 1219-1222 (2010).
5
An efficient tool for reliability improvement based on TMR (English)
Microelectronics Reliability 50, No. 9-11, 1247-1250 (2010).
6
On evaluating the signal reliability of self-checking arithmetic circuits (English)
SBCCI, 109-114 (2010).
7
AMS and RF design for reliability methodology (English)
ISCAS, 3657-3660 (2010).
8
Signal probability for reliability evaluation of logic circuits (English)
Microelectronics Reliability 48, No. 8-9, 1586-1591 (2008).
9
Relevant metrics for evaluation of concurrent error detection schemes (English)
Microelectronics Reliability 48, No. 8-9, 1601-1603 (2008).
10
Mixed-signal clock-skew calibration technique for time-interleaved adcs (English)
IEEE Trans. on Circuits and Systems 55-I, No. 11, 3676-3687 (2008).
11
A novel approach to non coherent UWB reception (English)
IMTIC, 100-109 (2008).
12
Yield and reliability issues in nanoelectronic technologies (English)
Annales des Télécommunications 61, No. 11-12, 1422-1457 (2006).
13
A CMOS implementation of time-interleaved high-pass delta sigma modulator (English)
ISCAS (2006).
14
High-pass delta sigma modulator: from system analysis to circuit design (English)
ISCAS (2006).
15
Systems-on-chip for telecommunications (English)
Annales des Télécommunications 59, No. 7-8, 755-758 (2004).
16
Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters (English)
SBCCI, 228-232 (2004).
17
Designing a programmable analog signal conditioning circuit without loss of measurement range (English)
IEEE T. Instrumentation and Measurement 52, No. 5, 1482-1487 (2003).
18
Analog to digital conversion: technical aspects (English)
Annales des Télécommunications 57, No. 5-6, 338-385 (2002).
19
A switched-current sample and hold circuit for low frequency applications (English)
ISCAS (1), 452-455 (2001).
20
Result 1 to 20 of 23 total
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