Result 1 to 20 of 221 total
An optimal boundary fair scheduling algorithm for multiprocessor real-time systems. (English)
J. Parallel Distrib. Comput. 71, No. 10, 1411-1425 (2011).
1
A novel scalable IPv6 lookup scheme using compressed pipelined tries. (English)
Domingo-Pascual, Jordi (ed.) et al., NETWORKING 2011. 10th international IFIP TC 6 networking conference, Valencia, Spain, May 9‒13, 2011. Proceedings, Part I. Berlin: Springer (ISBN 978-3-642-20756-3/pbk). Lecture Notes in Computer Science 6640, 406-419 (2011).
2
C-AMTE: A location mechanism for flexible cache management in chip multiprocessors. (English)
J. Parallel Distrib. Comput. 71, No. 6, 889-896 (2011).
3
Advanced hashing schemes for packet forwarding using set associative memory architectures. (English)
J. Parallel Distrib. Comput. 71, No. 1, 1-15 (2011).
4
Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM Main memory (English)
ISPASS, 56-65 (2011).
5
Two-hop free-space based optical interconnects for chip multiprocessors (English)
NOCS, 89-96 (2011).
6
Scalable multi-cache simulation using gpus (English)
MASCOTS, 159-167 (2011).
7
Energy-aware mappings of series-parallel workflows onto chip multiprocessors (English)
ICPP, 472-481 (2011).
8
A novel scalable IPv6 lookup scheme using compressed pipelined tries (English)
Networking (1), 406-419 (2011).
9
Impact of process variation on endurance algorithms for wear-prone memories (English)
DATE, 962-967 (2011).
10
Noc-aware cache design for multithreaded execution on tiled chip multiprocessors (English)
HiPEAC, 197-205 (2011).
11
Cache equalizer: a placement mechanism for chip multiprocessor distributed shared caches (English)
HiPEAC, 177-186 (2011).
12
A dynamic pressure-aware associative placement strategy for large scale chip multiprocessors (English)
Computer Architecture Letters 9, No. 1, 29-32 (2010).
13
On the interplay of parallelization, program performance, and energy consumption (English)
IEEE Trans. Parallel Distrib. Syst. 21, No. 3, 342-353 (2010).
14
Noc-aware cache design for chip multiprocessors (English)
PACT, 565-566 (2010).
15
An intra-tile cache set balancing scheme (English)
PACT, 549-550 (2010).
16
Compiler-assisted data distribution for chip multiprocessors (English)
PACT, 501-512 (2010).
17
Automated modeling and emulation of interconnect designs for many-core chip multiprocessors (English)
DAC, 431-436 (2010).
18
Applying statistical machine learning to multicore voltage \& frequency scaling (English)
Conf. Computing Frontiers, 277-286 (2010).
19
Increasing PCM Main memory lifetime (English)
DATE, 914-919 (2010).
20
Result 1 to 20 of 221 total
Start
Contact
Print
General Help
