Result 1 to 20 of 55 total
QR decomposition-based matrix inversion for high performance embedded MIMO receivers (English)
IEEE Transactions on Signal Processing 59, No. 4, 1858-1867 (2011).
1
Generic low-latency noc router architecture for FPGA computing systems (English)
FPL, 82-89 (2011).
2
Exploring virtual-channel architecture in FPGA based networks-on-chip (English)
SoCC, 302-307 (2011).
3
Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding (English)
IET Computers & Digital Techniques 4, No. 5, 349-364 (2010).
4
Evaluation of random delay insertion against DPA on fpgas (English)
TRETS 4, No. 1, 11 (2010).
5
Advanced multithreading architecture with hardware based scheduling (English)
FPL, 95-100 (2010).
6
TLM2.0 based timing accurate modeling method for complex noc systems (English)
ISCAS, 2900-2903 (2010).
7
Design and analysis of an advanced static blocked multithreading architecture (English)
SoCC, 169-173 (2010).
8
High-performance random data lookup for network processing (English)
SoCC, 272-277 (2010).
9
Is the differential frequency-based attack effective against random delay insertion? (English)
SiPS, 051-056 (2009).
10
DDR3 based lookup circuit for high-performance network processing (English)
SoCC, 351-354 (2009).
11
NFA decomposition and multiprocessing architecture for parallel regular expression processing (English)
SoCC, 347-350 (2009).
12
Guest editorial: Special issue on design and programming of signal processors for multimedia communication. (English)
J. VLSI Signal Process. 51, No. 3, 207-208 (2008).
13
From bit level systolic arrays to HDTV processor chips (English)
Signal Processing Systems 53, No. 1-2, 35-49 (2008).
14
Guest editorial: special issue on design and programming of signal processors for multimedia communication (English)
Signal Processing Systems 51, No. 3, 207-208 (2008).
15
Modified givens rotations and their application to matrix inversion (English)
ICASSP, 1437-1440 (2008).
16
Reduced-complexity MSGR-based matrix inversion (English)
SiPS, 124-128 (2008).
17
Differential power analysis of a SHACAL-2 hardware implementation (English)
ISCAS, 2933-2936 (2008).
18
Multi-standard sub-pixel interpolation architecture for video motion estimation (English)
SoCC, 229-232 (2008).
19
High performance IP lookup circuit using DDR SDRAM (English)
SoCC, 371-374 (2008).
20
Result 1 to 20 of 55 total