Result 1 to 20 of 24 total
A Multiple Seed Linear Feedback Shift Register. (English)
IEEE Transactions on Computers 41, No.02, 250-252 (1992).
1
A multiple seed linear feedback shift register (English)
IEEE Trans. Computers 41, No. 2, 250-252 (1992).
2
Testing for Coupled Cells in Random-Access Memories. (English)
IEEE Transactions on Computers 40, No.10, 1177-1180 (1991).
3
Testing for coupled cells in random-access memories (English)
IEEE Trans. Computers 40, No. 10, 1177-1180 (1991).
4
Testing for coupled cells in random-access memories (English)
ITC, 439-451 (1989).
5
Built-In Checking of the Correct Self-Test Signature. (English)
IEEE Transactions on Computers 37, No.09, 1142-1145 (1988).
6
Random Pattern Testability of Delay Faults. (English)
IEEE Transactions on Computers 37, No.03, 291-300 (1988).
7
Built-In Test for RAMs. (English)
IEEE Design and Test of Computers 05, No.04, 29-36 (1988).
8
Built-in checking of the correct self-test signature (English)
IEEE Trans. Computers 37, No. 9, 1142-1145 (1988).
9
Random pattern testability of delay faults (English)
IEEE Trans. Computers 37, No. 3, 291-300 (1988).
10
Identification of failing tests with cycling registers (English)
ITC, 322-328 (1988).
11
Fault propagation through embedded multiport memories. (English)
IEEE Trans. Comput. 36, No. 05, 592-602 (1987).
12
Fault propagation through embedded multiport memories. (English)
IEEE Trans. Comput. 36, 592-602 (1987).
13
Fault propagation through embedded multiport memories (English)
IEEE Trans. Computers 36, No. 5, 592-602 (1987).
14
Pseudorandom arrays for built-in tests. (English)
IEEE Trans. Comput. 35, No. 07, 653-658 (1986).
15
Pseudorandom arrays for built-in tests (English)
IEEE Trans. Computers 35, No. 7, 653-658 (1986).
16
Built-in checking of the correct self-test signature (English)
ITC, 54-59 (1986).
17
Random pattern testability of delay faults (English)
ITC, 263-273 (1986).
18
Random pattern testing for address-line faults in an embedded multiport memory (English)
ITC, 106-114 (1985).
19
Random pattern testing for data-line faults in an embedded multiport memory (English)
ITC, 100-105 (1985).
20
Result 1 to 20 of 24 total
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