Result 1 to 20 of 72 total
Throughput analysis for a high-performance FPGA-accelerated real-time search application. (English)
Int. J. Reconfig. Comput. 2012, Article ID 507173, 16 p. (2012).
1
A multi-ghz PLL built-in jitter extraction circuit for deep submicron technologies (English)
ECCTD, 657-660 (2011).
2
Design space exploration of Split-path data driven dynamic full adder. (English)
J. Low Power Electron. 6, No. 4, 469-481 (2010).
3
Radiation-hardened reconfigurable array with instruction roll-back (English)
Embedded Systems Letters 2, No. 4, 123-126 (2010).
4
Topology impact on the room temperature performance of thz-range ballistic deflection transistors (English)
ACM Great Lakes Symposium on VLSI, 159-162 (2010).
5
Design of self correcting radiation hardened digital circuits using decoupled ground bus (English)
ACM Great Lakes Symposium on VLSI, 405-408 (2010).
6
A C++-embedded domain-specific language for programming the MORA soft processor array (English)
ASAP, 141-148 (2010).
7
A new built-in IDDQ testing method using programmable BICS (English)
European Test Symposium, 264 (2010).
8
Novel programmable built-in current-sensor for analog, digital and mixed-signal circuits (English)
ISCAS, 3545-3548 (2010).
9
An area efficient design methodology for SEU tolerant digital circuits (English)
ISCAS, 981-984 (2010).
10
Implementing the blue midnight wish hash function on xilinx virtex-5 FPGA platform (English)
ReConFig, 394-399 (2010).
11
Power minimization methodology for VCTL topologies (English)
SoCC, 330-333 (2010).
12
Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems. (English)
J. Low Power Electron. 5, No. 3, 326-338 (2009).
13
Energy efficient coarse-grain reconfigurable array for accelerating digital signal processing. (English)
Svensson, Lars (ed.) et al., Integrated circuit and system design. Power and timing modeling, optimization and simulation. 18th international workshop, PATMOS 2008, Lisbon, Portugal, September 10‒12, 2008. Revised selected papers. Berlin: Springer (ISBN 978-3-540-95947-2/pbk). Lecture Notes in Computer Science 5349, 297-306 (2009).
14
A low cost reconfigurable soft processor for multimedia applications: design synthesis and programming model (English)
FPL, 534-538 (2009).
15
Programming model and low-level language for a coarse-grained reconfigurable multimedia processor (English)
ERSA, 195-201 (2009).
16
Varicap threshold logic (English)
ACM Great Lakes Symposium on VLSI, 239-244 (2009).
17
Study of leakage current mechanisms in ballistic deflection transistors (English)
ACM Great Lakes Symposium on VLSI, 165-168 (2009).
18
A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic (English)
ACM Great Lakes Symposium on VLSI, 433-436 (2009).
19
New performance/power/area efficient, reliable full adder design (English)
ACM Great Lakes Symposium on VLSI, 493-498 (2009).
20
Result 1 to 20 of 72 total
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